原创 【心得笔记】FPAG pipeline RISC设计(1) -- FPGA设计和ASIC设计常用单元

FPAG pipeline RISC设计(1) -- FPGA设计和ASIC设计常用单元代价对比<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

Area Cost

ITEM           ASIC      FPGA

Memory      High       Medium

Multiplier    High        Medium

Registers   Medium   Low

Adders       Medium   Low

Multiplexer Low        High

. FPGA Hard optimization:

Memory, Multiplier

. FPGA rich registers with every lookup-table

. Multiplexer implemented in look-up table for FPGA