原创 硬件接口定义规范-III

接口卡的外观<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

Pin

+5V

+3.3V

Universal

Description

A1

TRST

Test Logic Reset

A2

+12V

+12 VDC

A3

TMS

Test Mde Select

A4

TDI

Test Data Input

A5

+5V

+5 VDC

A6

INTA

Interrupt A

A7

INTC

Interrupt C

A8

+5V

+5 VDC

A9

RESV01

Reserved VDC

A10

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

A11

RESV03

Reserved VDC

A12

GND03

(OPEN)

(OPEN)

Ground or Open (Key)

A13

GND05

(OPEN)

(OPEN)

Ground or Open (Key)

A14

RESV05

Reserved VDC

A15

RESET

Reset

A16

+5V

+3.3V

Signal Rail

+V I/O (+5 V or +3.3 V)

A17

GNT

Grant PCI use

A18

GND08

Ground

A19

RESV06

Reserved VDC

A20

AD30

Address/Data 30

A21

+3.3V01

+3.3 VDC

A22

AD28

Address/Data 28

A23

AD26

Address/Data 26

A24

GND10

Ground

A25

AD24

Address/Data 24

A26

IDSEL

Initialization Device Select

A27

+3.3V03

+3.3 VDC

A28

AD22

Address/Data 22

A29

AD20

Address/Data 20

A30

GND12

Ground

A31

AD18

Address/Data 18

A32

AD16

Address/Data 16

A33

+3.3V05

+3.3 VDC

A34

FRAME

Address or Data phase

A35

GND14

Ground

A36

TRDY

Target Ready

A37

GND15

Ground

A38

STOP

Stop Transfer Cycle

A39

+3.3V07

+3.3 VDC

A40

SDONE

Snoop Done

A41

SBO

Snoop Backoff

A42

GND17

Ground

A43

PAR

Parity

A44

AD15

Address/Data 15

A45

+3.3V10

+3.3 VDC

A46

AD13

Address/Data 13

A47

AD11

Address/Data 11

A48

GND19

Ground

A49

AD9

Address/Data 9

A52

C/BE0

Command, Byte Enable 0