原创 【笔记】《Finite State Machine Datapath Design》重要概念-2

part2

CHAPTER 2
Improving Design Performance

Maximize the clock frequency by adding output registers

Example1：

Minimize the setup and hold window by adding input registers

add output register:

  tsu_TOTAL= (tpd_data_U1- tpd_clk_U1)) + tsu_FF=(18 - 2) + 3 = 19 ns

  thd_TOTAL= (tpd_clk(MAX) - tpd_data(MIN)) + tsu_FF=(2 - 8) + 4 = -2ns

add output register:

  tsu_TOTAL= (tpd_data_U1 - tpd_clk_U1)) + tsu_FF=(1 - 2) + 3 = 2ns

  thd_TOTAL= (tpd_clk(MAX)- tpd_data(MIN)) + tsu_FF=(2 - 1) + 4 = 5ns

Use DLL/PLL to eliminate clock skew