一个论文-A 2-5GHz Low Jitter 0.13u...
时间:2020-01-14
大小:554.17KB
阅读数:146
查看他发布的资源
资料介绍
A 2-5GHz Low Jitter 0IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE
A 2-5GHz Low Jitter 0.13p.m CMOS PLL Using a Dynamic Current Matching Charge-pump and a Noise Attenuating Loop-Filter
Adrian Maxim
Integrated Products, 4201 Monterey Oaks #612, Austin TX 78749, Email: adrianmaxim@ieee.org
Abstract A low noise ring oscillator based PLL frequency synthesizer was realized for wideband tuner applications. The reference spurs are minimized using a fast reset, precharged phase-frequency-detector and a dynamic current matching charge-pump. The PLL has a single power supply, while a shunt regulator was used to bias the digital blocks without coupling noise to the analog supply. A two stage symmetric NFET load ring oscillator was used for both low phase noise and high frequency operation. A noise attenuating loop fi……
版权说明:本资料由用户提供并上传,仅用于学习交流;若内容存在侵权,请进行举报,或
联系我们 删除。