一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文档。文件列表: embedded_risc .............\Machine_Language .............\................\program.txt .............\SOC_Design.pdf .............\Test_Bench_Verilog .............\..................\Top_level_tb.tf .............\Verilog .............\.......\ACC.V .............\.......\ALU.V .............\.......\bus_arbiter.v .............\.......\cmd_ack.v .............\.......\cmd_decoder.v .............\.......\cmd_detector.v .............\.......\cmd_generator.v .............\.......\cmd_internal_reg.v .............\.......\command_if.v .............\.......\CONTROL.V .............\.......\data_cache_way0.v .............\.......\data_cache_way1.v .............\.......\data_cache_way2.v .............\.......\data_cache_way3.v .............\.......\data_in_reg.v .............\.......\data_port.v .............\.......\dma_cntrl.v .............\.......\dma_fifo.v .............\.......\dma_internal_reg.v .............\.......\flash_ctrl.v .............\.......\fsm.v .............\.......\instruction_cache_way0.v .............\.......\instruction_cache_way1.v .............\.......\instruction_cache_way2.v .............\.......\instruction_cache_way3.v .............\.......\IR.V .............\.......\k9f1g08u0m.v .............\.......\lru_data_cache.v .............\.......\lru_instruction_cache.v .............\.......\MEM.V .............\.......\MUX12.V .............\.......\MUX16.V .............\.......\oe_generator.v .............\.......\parameter.v .............\.......\PC.V .............\.......\ras_cas_delay.v .............\.......\ref_ack.v .............\.......\ref_timer.v .............\.......\risc.v .............\.......\sdram.v .............\.......\sdramctrl_rtl.v .............\.......\sdram_cntrl.v .............\.......\sdram_mux.v .............\.......\sdram_port.v .............\.......\soc.v .............\.......\timer.v .............\.......\uart.v……