标签: buffer

我目前就搞搞简单的时钟、表盘应用，需要高刷和低占用的，估计用fbdev更简单 如果你需要在一个简单的时钟、表盘应用程序中使用高刷新率和低占用的解决方案，使用fbdev是一个不错的选择。fbdev是一个Linux内核帧缓冲设备（Frame Buffer Device）的接口，它提供了一个在内存中直接操作显示缓冲区的方法。 使用fbdev可以让你直接在内存中绘制图形，而不需要通过X Window System或Wayland等图形界面库。这使得它在低占用的同时，也具有了较高的刷新率。 下面是使用fbdev的一般步骤： 安装内核帧缓冲设备驱动程序：在大多数Linux发行版中，fbdev驱动程序已经预装。如果没有预装，你可以通过相应的软件包管理器安装它。 获取fbdev设备文件：在大多数Linux系统中，fbdev设备文件通常被命名为/dev/fb0。你可以使用ls /dev/命令来查找它。 配置显示参数：在使用fbdev之前，你需要设置正确的显示参数。这包括分辨率、颜色深度和刷新率等。你可以使用fbset命令或者直接在X Window System中设置这些参数。 编写应用程序代码：使用C语言或其他编程语言编写应用程序代码。你可以使用系统提供的API来访问fbdev设备文件，并直接在内存中绘制图形。 编译和运行应用程序：使用适当的编译器将应用程序代码编译为可执行文件，并确保你的系统具有执行权限。然后运行可执行文件，你的应用程序就会在fbdev上显示出来。 需要注意的是，如果你希望在应用程序中实现高刷新率，你需要确保你的代码能够在短时间内完成绘制操作，以避免屏幕闪烁或图像撕裂等问题。此外，你还需要注意管理显示内存的使用，以避免不必要的资源浪费。 希望这可以帮助你开始使用fbdev来开发简单的时钟、表盘应用程序。如果你需要更详细的信息或具体的代码示例，请随时提问。

Full HD FIFO DRAM,(AVERLOGIC AL460)顾名思义就是应用于两个主动组件之间的影像暂储存内存.当Write enable写入智能脚位工作启动时,Read-clock 写入频率输入同步启动时,那影像的数据(video data)就会从低到高位输入.在FIFO内部,内存的Address就会从write pointer (写入指标)到read pointer(读出指标)依序排列.当每个读出指标完成动作后,读出指标就会到下一个内存地址继续工作.若在reset 重置状况下,两者指标(write pointer, read pointer) 就会回到第一个内存地址.   联系人： 龚先生（茂晶骏龙有限公司） 电话：86755-8828-5788 邮箱：DragonG@gfei.com.hk  

In my previous blog , I mentioned that I've been invited to give a guest lecture at the ITT Technical Institute in Alabama, United States. As part of this talk, which is planned for the evening of July 29, I want to give the students some real "hands-on" experience—seeing and touching things like relays and vacuum tubes and so forth. Now, I do have a couple of relays lying around here in my office (who doesn't?), but these little scamps tend to be relatively modern—being presented in transparent plastic packages, for example—which doesn't convey quite the sort of impression I'm hoping to achieve. Thus it was that, on my way into work this morning, I took a detour via that downtown electronics wonderland known as Mock Electronics. If truth be told, I'm happy for any excuse to visit the folks at Mock Electronics to discover any new antique delights with which they invariably tempt me. When I explained what I was planning with regard to my talk and asked if they happened to have any old relays lying around, I certainly wasn't surprised when they whipped out the little beauty you see below.   First of all we have the coil, which is wound around a soft iron core, and which can be energized using the two contacts "C1" and C2" (when I returned to my office, my chum Ivan immediately hooked this little beauty up to his power supply and we discovered that it switches at around 4V and consumes only 20mA; based on this, we assume it was actually intended for 5V operation). Next, we have an iron yoke, which provides a low reluctance path for the magnetic flux. Then we have the armature, which pivots around the left-hand side of the yoke. When no voltage is applied to the coil, a spring pulls the armature such that it is held against contact "A." This means that whatever voltage value is being presented to "input" contact "A" is conducted through the armature to "output" contact "Y." When the coil is energized, it attracts the end of the armature in the upper portion of this image, pulling it to the right. Since the armature pivots around the yoke, this causes the end of the armature in the lower portion of this image to move to the left, thereby disengaging from contact "A" and pressing against contact "B." Now, whatever voltage value is being presented to "input" contact "B" is conducted through the armature to "output" contact "Y." The wonderful thing about the relay in the image above is that it offers such a beautiful combination of simplicity (of function) and sophistication (of implementation). Observe how everything can be quickly and easily adjusted, such as the positions of the contacts and the tension on the spring. Depending on how you wire this up, it could act as a simple isolating buffer, where output "Y" = 0V (logic 0) if the coil is not energized or 5V (logic 1) if the coil is energized; or as an inverter, where output "Y" = 5V (logic 1) if the coil is not energized or 0V (logic 0) if the coil is energized. From this, we could construct AND, OR, NAND, and NOR gates; then XOR and NXOR gates; and then registers and so forth. Yes, of course, you know me so well... now I'm being carried away with dreams of getting several thousand of these little beauties and using them to construct something like a simple 4bit processor, but that's something we can talk about on a future occasion... Let's return to the problem of implementing logic gates and registers using only the type of relay shown in the image above. If you haven't worked with relays before, I bet your knee-jerk reaction is to think of using them in much the same way you might use transistor switches, but—generally speaking—it's not quite that simple. As you will soon discover, constructing logical functions using relays can involve a weird and wonderful mixture of simplicity and complexity; if nothing else, it encourages a lot of "out-of-the-box" thinking. Now, rather than me just waffling on and explaining everything in excruciating, let's have some fun with this. As a starting point, can you come up with a circuit symbol and truth table that clearly and concisely represents the operation of this relay? (Please feel free to change the names of the various contacts I called "A," "B,", "Y," "C1," and "C2" to whatever you like if it better suits your purpose.) Based on this, can you create a circuit diagram for a single buffer and then for three of these buffers connected in series? Next, can you create a circuit diagram for a single inverter and then for three of these inverters connected in series. How about creating a circuit diagram for 2-input AND, NAND, OR and NOR gates (a) in isolation, (b) driving one of your buffer gates, and (c) driving one of your inverter gates? Let's leave things here for the moment. If you rise to this challenge, then we'll move on to consider how we might set about implementing register and memory elements.  

I think I may have "over-indulged" several days ago whilst watching the Super Bowl. I was certainly "relaxed and refreshed and feeling no pain," as it were. The problem is that things all seem to be a little "fluffy" around the edges the morning after. I'm finding it a tad difficult to get my brain to go into gear – it's like trying to fire-up a car that doesn't want to start – you keep on turning the key and the engine sort of splutters into life – and then it judders to a graunching halt again. This might explain why I'm having so much difficulty wrapping my brain around a question that came winging its way across the Internet to me that day. But first, let's set the scene. In Chapter 6 of my book Bebop to the Boolean Boogie: An Unconventional Guide to Electronics (still the only electronics book in the world to include a Seafood Gumbo recipe) we consider how to construct primitive logic gates using CMOS technology (PMOS and NMOS transistors connected together in a complementary manner).   We start off with a simple inverter function in the form of a NOT (or INV) gate as shown below. If input 'a' is presented with a logic 0 (for example, if we used a wire to connect it to the VSS line), then NMOS transistor Tr2 will be turned Off, PMOS transistor Tr1 will be turned On, and output 'y' will be connected to VDD (logic 1) via Tr1.   Similarly, if input 'a' is presented with a logic 1 (for example, if we used a wire to connect it to the VDD line), then PMOS transistor Tr1 will be turned Off, NMOS transistor Tr2 will be turned On, and output 'y' will be connected to VSS (logic 0) via Tr2. I then go on to explain that a non-inverting BUF (buffer) gate is more complex than a NOT gate. This is due to the fact that a BUF gate is essentially constructed from two NOT gates connected in series as shown below:   So far, so good. But now we move to consider the email I received, which reads as follows: Respected sir, I read your book "Bebop to the Boolean Boogie" and found it really amazing. The matter has been presented in a very friendly tone and easy to understand style. It really helped me to thoroughly understand the concepts. But, I would like to bring into your consideration a small mistake from the book. In the chapter 'Using Transistors to Build Primitive Logic Functions' it is written that for building a CMOS Buffer, four transistors are required. But i think, interchanging the positions of the NMOS and PMOS transistors in the NOT circuit (given in the book) can give a Buffer and this technique uses only two transistors. Please find an image file attached with this email with a circuit diagram.   Am I right? Or is there a flaw in the above technique? Except for this, I found the book very good and I will surely recommend it to my peers. Thank you sir for your consideration. Well, you have to admit that he writes a very nice message. So there I am sitting looking at his suggested circuit. I can absolutely see where he's coming from. At the same time, I know this won't work, because I know you can't connect the PMOS and NMOS transistors together in this way. The problem is that – as I mentioned above – my poor old brain is limping along at a fraction of its usual speed, and I find myself unable to articulate why this won't work. What say you? How can we put this into words that he (and I) will understand?