原创 BMD参考设计层次结构（7x）

PIO example design is provided to exercise only basic core functionality. It has very small BRAMs (back-end memory) and will only respond to 1DW payload data (4 Bytes) per packet. Anything larger (or burst) is not supported.

Below are some details of the PIO example design:

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1. The PIO design is a simple target-only application that interfaces with the Endpoint for PCIe cores Transaction (TRN) interface.
2. The PIO design only supports single DWORD payload Read and Write PCI Express transactions to 32/64 bit address memory spaces and IO space with support for completion TLPs.
3. The example design supports one IO space BAR, one 32-bit Memory space (that cannot be the Expansion ROM space), and one 64-bit Memory space. If these limits are exceeded, only the first space of a given type will be activeaccesses to the other spaces will not result in completions.
4. Each space is implemented with a 2 kB memory. If the corresponding BAR is configured to a wider aperture, accesses beyond the 2 kB limit wrap around and overlap the 2 kB memory space.
5. The PIO design successfully processes single DWORD payload Memory Read and Write TLPs and IO Read and Write TLPs. Memory Read or Memory Write TLPs of lengths larger than one DWORD are not processed correctly by the PIO design; however, the core does accept these TLPs and passes them along to
the PIO design. If the PIO design receives a TLP with a length of greater than 1 DWORD, the TLP is received completely from the core and discarded. No corresponding completion is generated.
6. PIO design handles Memory writes and IO TLP writes in different ways: the PIO design responds to IO writes by generating a Completion Without Data (cpl), a requirement of the PCI Express specification.
7. The PIO_32_TX_ENGINE and PIO_64_TX_ENGINE modules generate completions for received memory and IO read TLPs. The PIO design does not generate outbound read or write requests. However, users can add this functionality to further customize the design.

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