原创 基于ALTERA Cyclone 10器件的LVDS接收模块例化遇到的问题

概述

本文主要记录在实际使用FPGA的LVDS模块初始阶段时候遇到的问题，这些问题都是些非典型问题。

C10器件LVDS-RX对接M10器件LVDS-TX遇到的问题

因为板子上有一片C10和一片M10器件，而且电路设计的时候安排了两个器件之间的LVDS接口连接。所以在C10与ADC对接之前，首先在C10与M10之间进行LVDS接口调试，这样可以将C10的LVDS-RX移植到与ADC采样数据的接口。

由于M10与FPGA之间并未安排随路时钟，所以打算使用FPGA的系统时钟来作为LVDS-RX的参考输入时钟。直接例化LVDS-RX后编译的时候遇到问题，在Fit的时候会出现如下所示的报错信息：

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 LVDS_CLOCK_TREE(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.

Error (175020): The Fitter cannot place logic LVDS_CLOCK_TREE that is part of LVDS SERDES Intel FPGA IP LVDS_1Ch6B_RX_altera_lvds_2001_3ymtrna in region (38, 32) to (38, 32), to which it is constrained, because there are no valid locations in the region for logic of this type.

Info (14596): Information about the failing component(s):

Info (175028): The LVDS_CLOCK_TREE name(s): u_LVDS_RX_Test|LVDS_1Ch6B_RX_inst|lvds_0|core|arch_inst|default_lvds_clock_tree.lvds_clock_tree_inst

Error (16234): No legal location could be found out of 2 considered location(s). Reasons why each location could not be used are summarized below:

Info (175013): The LVDS_CLOCK_TREE is constrained to the region (38, 32) to (38, 32) due to related logic

Info (175015): The I/O pad clkin is constrained to the location PIN_AA18 due to: User Location Constraints (PIN_AA18) File: E:/won/CSEP/C10GX_AD9633/src/C10GX_AD9633.vhd Line: 19

Info (14709): The constrained I/O pad drives a IOPLL, which drives this LVDS_CLOCK_TREE

Error (175006): There is no routing connectivity between the LVDS_CLOCK_TREE and destination LVDS_CHANNEL

Info (175027): Destination: LVDS_CHANNEL u_LVDS_RX_Test|LVDS_1Ch6B_RX_inst|lvds_0|core|arch_inst|channels[0].rx_non_dpa.serdes_dpa_inst~CHANNEL

Info (175015): The I/O pad M10_TO_C10_LVDS_RX is constrained to the location PIN_P3 due to: User Location Constraints (PIN_P3) File: E:/won/CSEP/C10GX_AD9633/src/C10GX_AD9633.vhd Line: 29

Info (14709): The constrained I/O pad is contained within a pin, which is contained within this LVDS_CHANNEL

Error (175022): The LVDS_CLOCK_TREE could not be placed in any location to satisfy its connectivity requirements

Info (175021): The destination LVDS_CHANNEL was placed in location LVDS_CHANNEL containing P3

Info (175029): 2 locations affected

Info (175029): LVDSCLOCKTREE_X38_Y32_N4

Info (175029): LVDSCLOCKTREE_X38_Y32_N5

Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.

Error (16297): An error has occurred while trying to initialize the plan stage.

Error: Quartus Prime Fitter was unsuccessful. 7 errors, 2 warnings

Error: Peak virtual memory: 1397 megabytes

Error: Processing ended: Mon Jul 29 17:45:25 2024

Error: Elapsed time: 00:00:09

Error: System process ID: 12428

后来检查发现该时钟输入引脚与LVDS-RX的引脚位于FPGA的不同bank，如图1所示，所以LVDS-RX例化时需要打开external PLL选项，如图2所示。

图1：LVDS-RX引脚与其参数输入时钟引脚位于FPGA的不同BANK

图2：LVDS-RX例化时PLL设置

如图2所示，LVDS模块例化的时候可以选择使用外部PLL。但是在设计C10与M10之间的LVDS通信的时候，即便因为上述原因使用外部PLL，依然未成功，因为FPGA主时钟输入I/O标准是单端的LVCMOS，LVDS模块似乎仅支持LVDS差分标准。

由于这对C10与M10之间的LVDS差分对正好与ADC差分对接入同一个FPGA的bank，所以在例化的时候，将LVDS-RX的参考输入时钟直接接入ADC的FCO，这样就成功了，可以实现M10串行发送，而C10进行串行接收。

根据正常理解，LVDS数据线可以与参考时钟位于不同的BANK，只是此时必须使用外部PLL形式。上述示例并未验证是否可行，因为如图1所示的不同bank的时钟是单端输入，应该是无法直接用作LVDS的参考时钟。另外，也尝试进行PLL级联，即在例化LVDS模块的时候，并未选择图2中“Use external PLL”，LVDS模块直接内置PLL，外部再例化一个PLL使用该单端时钟，再使用PLL的输出时钟来作为LVDS的参考时钟，但是这样使用并未获得通过，在编译的时候会出现下述报错信息。

Error (18694): The reference clock on PLL "u_LVDS_RX_Test|LVDS_1Ch10B_RX_inst|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

Error: Failed to synthesize partition

Error: Quartus Prime Synthesis was unsuccessful. 2 errors, 22 warnings

Error: Peak virtual memory: 726 megabytes

Error: Processing ended: Mon Jul 29 15:20:58 2024

Error: Elapsed time: 00:00:39

Error: System process ID: 4044

参考

1. LVDS SERDES Intel FPGA IP User Guide: Intel Arria 10 and Intel Cyclone 10 Devvices.