原创 DIR chromatrope(2)

板子焊好了，没有支架，手拿着转了一会，电机震动很大，还冒了冒小烟，胆小，没敢再转。

芯片用的是EPM240T100，用了40个io口，如果用mcu，这么多的io口也不经济。

40个io转动起来应该有80*80 的效果吧。

到电子市场淘了个直流12v的电机，要转速最高的，卖的人说是12000转/分钟。如果他说的是实情，则每秒有200转，5ms/转。如果每转分360度，则每一度是13.8us。用ns级的cpld来运行就很轻松了，

等pcb回来，才发现上面有好多低级错误，这还不严重，毕竟是试验板吗，大不了连连线。等焊接好元件才发现，板子很不平衡，这才恍然为什么别人的板为什么是一头错来一头细。没办法，只好在轻的一头添加热融胶，加了好多，芯片都淹没了，最后还沾上了2个硬币才勉强平衡。

测试霍尔元件后，又感觉不对了，44e电压4.5~12v的，且感应距离很短，磁石要靠的很近才能动作。对于我手工的来说，要达到这个精度是有点麻烦的。

module led1(
   clk,rst_n,
   sensor,dis, 
   ledtest
  );

input clk;  / / 50MHz
input rst_n;          // 复位信号，低有效
input sensor;
output[39:0] dis; 
output ledtest;         //temp
//----------------------------------------------------------------------------

//----------------------------------------------------------------------------
reg sensor0,sensor1,sensor2;
wire neg_sensor;
always @ (posedge clk or negedge rst_n) begin
 if(!rst_n) begin
   sensor0 <= 1'b0;
   sensor1 <= 1'b0;
   sensor2 <= 1'b0;
   
  end
 else begin
   sensor0 <= sensor;
   sensor1 <= sensor0;
   sensor2 <= sensor1;
  end
end
assign neg_sensor =  ~sensor1 & sensor2;  // 检测下降沿
reg flag_sensor;
always @ (posedge clk or negedge rst_n)
 if (!rst_n) flag_sensor <= 1'b0;
 else if (neg_sensor) flag_sensor <= 1'b1;
//---------------------------------------------------------------------------
reg[17:0] time_cnt; //计数器，13888ns ＝＝10H2B6
always @ (posedge clk or negedge rst_n)
 if(!rst_n) time_cnt <= 18'd0;
 else if (time_cnt == 18'h3ffff) time_cnt <= 10'd0;//698
 else time_cnt <= time_cnt + 1'b1;   //每20ns加1
 
reg testled_r; 
reg[5:0] dis_cnt;         //显示循环，暂时显示32个列
always @ (posedge clk or negedge rst_n)begin
 if(!rst_n)begin
        dis_cnt <= 6'd0;
   testled_r <= 1'b1;
   end
 else if (time_cnt == 18'h3ffff)begin
      // time_cnt <= 10'd0;
       dis_cnt <= dis_cnt + 1'b1;    // 每13888ns显示下一列。
        testled_r <= ~testled_r;
       if (dis_cnt[5]) dis_cnt <= 6'd0;
   
    end
 
end
assign  ledtest = testled_r;
//---------------------------------------------------------------------------
reg[39:0] dis_r;   
always @ (posedge clk or negedge rst_n)
begin
case(dis_cnt)
  8'd0: dis_r = 40'h0000000000;
  8'd1: dis_r = 40'h0000000000;
  8'd2: dis_r = 40'h1FE0000000;
  8'd3: dis_r = 40'h0FC0000000;
  8'd4: dis_r = 40'h0840000000;
  8'd5: dis_r = 40'h0840000000;
  8'd6: dis_r = 40'h8400000000;
  8'd7: dis_r = 40'hFFF0000000;
  8'd8: dis_r = 40'h7FFE000000;
  8'd9: dis_r = 40'h0840000000;
  8'd10:dis_r = 40'h0840000000;
  8'd11:dis_r = 40'h0840000000;
  8'd12:dis_r = 40'h0FE0000000;
  8'd13:dis_r = 40'h1FC0000000;
  8'd14:dis_r = 40'h0800000000;
  8'd15:dis_r = 40'h0000000000;
  
  8'd16:dis_r = 40'h0000000000;
  8'd16:dis_r = 40'h0000000000;
  8'd16:dis_r = 40'hFFFF000000;
  8'd16:dis_r = 40'h7FFE000000;
  8'd16:dis_r = 40'h400A000000;
  8'd16:dis_r = 40'h490A000000;
  8'd16:dis_r = 40'h490A000000;
  8'd16:dis_r = 40'h4FFA000000;
        8'd16:dis_r = 40'h4FFA000000;
        8'd16:dis_r = 40'h49CA000000;
        8'd16:dis_r = 40'h5B7A000000;
        8'd16:dis_r = 40'h492A000000;
        8'd16:dis_r = 40'h400A000000;
        8'd16:dis_r = 40'h7FFF000000;
        8'd16:dis_r = 40'hFFFE000000;
        8'd16:dis_r = 40'h4000000000;
endcase
end
assign dis = dis_r;       
 
endmodule