High-Speed Board Design Techniques
(Introduction to CAD)
naehyuck@snu.ac.kr
March 5, 1999
1 Introduction
Speed is one of the most important design factor
– Hundreds of MHz processors are available
Demand for short propagation delay
– Fast edge rate is required
– Results in ringing, reflections, and crosstalk
2 What to cover
Power distribution system
Transmission line and associated design rules
Crosstalk and its elimination
Electromagnetic interference
Reference: High-Speed Board Design Techniques, Vantis, Aug., 1997.
1
Dept. of Computer Engineering, Seoul National University 2
Load
Vcc
a) Ideal power source: zero line impedance
V+ Load
b) Realistic power source: non-zero line impedance
V+
Figure 1: The power source
3 Power distribution system
Noise-free power distribution network
Vcc is as important as Ground
For AC purpose, Vcc is ground
The design goal ! Reduce the power distribution network impedances as
much as possible
3.1 Power plane versus power bus
3.2 Line noise filtering
Power plane alone does not eliminate line noise
Generally, 1uF to 10uF across the power input
Dept. of Computer Engineering, Seoul National University 3
Power Bus Power plane
Figure 2: Power distribution system: power bus vs. power plane
a) Ideal
b) real condition
Figure 3: Capacitor: ideal and real condition
Generally, 0.01uF to 0.1uF across every power pin of active devices
Larger capacitors: 10F
– Filter low frequencies (60Hz) that usually are generated off the board
Small capacitors: 0.1F
– High frequencies (100MHz and higher)
Equivalent-series resistance (ESR) and equivalent-series inductance (ESL)
Resonant frequency
fR =
1
pLC
Dept. of Computer Engineering, Seoul National University 4
Capacitive Inductive
f
R
Z
C
Capacitive Inductive
f
R
Z
C
Figure 4: Capacitance impedance versus frequency and the effect of lowering
capacitance while using the same type of construction (constant ESL)
– fR of large capacitors ( F) is generally less than 1MHz
ESL and ESR result from the construction of the capacitor and dielectric
material used, rather than from capacitance value
3.3 Bypass capacitor placement
Lead extensions on non-power planes
Internally separated power pins must be decoupled individually
Dept. of Computer Engineering, Seoul National University 5
Table 1: Bypass capacitor group
Type Range of Interest Applications
Electrolytic 1 F to > 20 F Power supply connection on board
Ceramic 0.01 F to 0.1 F At the chip
C0G < 0.1 F Noise-sensitive devices
0.1 1.0 10.0 100.0 1K
0.001
0.010
0.100
1.000
10.000
100.000
Z
C
f
R
f
R
MHz
Figure 5: Frequency response of X7R and C0G type construction
0.1 1.0 10.0 100.0 1K
0.001
0.010
0.100
1.000
10.000
100.000
f
R
f
R
MHz
Figure 6: Frequency response of two capacitors in parallel
Dept. of Computer Engineering, Seoul National University 6
Figure 7: Bypass capacitor placement
3.4 Power distribution network as a signal return path
Natural path of the signal-return line
Current loop inductance can be thought of as single-turn coils
Current loop inductance increases with loop size
Minimize loop size!minimize problems
The inductance of a signal line and its return line increases with the separation
of the two paths. ! The path of least impedance is the path bringing
the signal-return line closest to the signal line.
In multiple layer boards, “as close as possible” means in a ground or Vcc
plane above or below the signal trace.
Bus vs. planes for a signal-return path
L = Kl ln
d
(Introduction to CAD)
naehyuck@snu.ac.kr
March 5, 1999
1 Introduction
Speed is one of the most important design factor
– Hundreds of MHz processors are available
Demand for short propagation delay
– Fast edge rate is required
– Results in ringing, reflections, and crosstalk
2 What to cover
Power distribution system
Transmission line and associated design rules
Crosstalk and its elimination
Electromagnetic interference
Reference: High-Speed Board Design Techniques, Vantis, Aug., 1997.
1
Dept. of Computer Engineering, Seoul National University 2
Load
Vcc
a) Ideal power source: zero line impedance
V+ Load
b) Realistic power source: non-zero line impedance
V+
Figure 1: The power source
3 Power distribution system
Noise-free power distribution network
Vcc is as important as Ground
For AC purpose, Vcc is ground
The design goal ! Reduce the power distribution network impedances as
much as possible
3.1 Power plane versus power bus
3.2 Line noise filtering
Power plane alone does not eliminate line noise
Generally, 1uF to 10uF across the power input
Dept. of Computer Engineering, Seoul National University 3
Power Bus Power plane
Figure 2: Power distribution system: power bus vs. power plane
a) Ideal
b) real condition
Figure 3: Capacitor: ideal and real condition
Generally, 0.01uF to 0.1uF across every power pin of active devices
Larger capacitors: 10F
– Filter low frequencies (60Hz) that usually are generated off the board
Small capacitors: 0.1F
– High frequencies (100MHz and higher)
Equivalent-series resistance (ESR) and equivalent-series inductance (ESL)
Resonant frequency
fR =
1
pLC
Dept. of Computer Engineering, Seoul National University 4
Capacitive Inductive
f
R
Z
C
Capacitive Inductive
f
R
Z
C
Figure 4: Capacitance impedance versus frequency and the effect of lowering
capacitance while using the same type of construction (constant ESL)
– fR of large capacitors ( F) is generally less than 1MHz
ESL and ESR result from the construction of the capacitor and dielectric
material used, rather than from capacitance value
3.3 Bypass capacitor placement
Lead extensions on non-power planes
Internally separated power pins must be decoupled individually
Dept. of Computer Engineering, Seoul National University 5
Table 1: Bypass capacitor group
Type Range of Interest Applications
Electrolytic 1 F to > 20 F Power supply connection on board
Ceramic 0.01 F to 0.1 F At the chip
C0G < 0.1 F Noise-sensitive devices
0.1 1.0 10.0 100.0 1K
0.001
0.010
0.100
1.000
10.000
100.000
Z
C
f
R
f
R
MHz
Figure 5: Frequency response of X7R and C0G type construction
0.1 1.0 10.0 100.0 1K
0.001
0.010
0.100
1.000
10.000
100.000
f
R
f
R
MHz
Figure 6: Frequency response of two capacitors in parallel
Dept. of Computer Engineering, Seoul National University 6
Figure 7: Bypass capacitor placement
3.4 Power distribution network as a signal return path
Natural path of the signal-return line
Current loop inductance can be thought of as single-turn coils
Current loop inductance increases with loop size
Minimize loop size!minimize problems
The inductance of a signal line and its return line increases with the separation
of the two paths. ! The path of least impedance is the path bringing
the signal-return line closest to the signal line.
In multiple layer boards, “as close as possible” means in a ground or Vcc
plane above or below the signal trace.
Bus vs. planes for a signal-return path
L = Kl ln
d
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