N_even_divider.v / Verilog
module N_bit_even_divider (
output reg o_clk,
input i_clk,
input rst_n
);
parameter N = N_even; // 设置偶数倍分频
parameter M = ?; // M="N/2-1"
// bit_of_N: N_even的二进制位宽
reg [(bit_of_N - 1):0] cnt; // 计数器单元
reg [(bit_of_N - 1):0] cnt; // 计数器单元
// 上升沿计数: 0~(N-1)
always @ (posedge i_clk, negedge rst_n)
begin
if (!rst_n)
cnt <= 0;
else
begin
if (cnt == N-1)
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
end
always @ (posedge i_clk, negedge rst_n)
begin
if (!rst_n)
cnt <= 0;
else
begin
if (cnt == N-1)
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
end
// 生成上升沿时钟
// 0~(N/2-1) ↑ -> 1; (N/2)~(N-1) ↑ -> 0
always @ (posedge i_clk, negedge rst_n)
begin
if (!rst_n)
o_clk <= 0;
else
begin
if (cnt <= M)
// 0~(N/2-1) ↑ -> 1; (N/2)~(N-1) ↑ -> 0
always @ (posedge i_clk, negedge rst_n)
begin
if (!rst_n)
o_clk <= 0;
else
begin
if (cnt <= M)
o_clk <= 1;
else
o_clk <= 0;
end
end
else
o_clk <= 0;
end
end
endmodule
仿真波形
图1. N_bit_even = 2, (bit_of_N - 1)取1或0)
图2. N_even = 2, (bit_of_N - 1)取2)
图3. N_even = 4
图4. N_even = 6
另见
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