原创 [原创]一些有用的Verilog程序

串并转化模块(都是自己写的,大家不要笑啊)

module ps(par_d,
ps_flag,
d_in,
rst,
clk,
dout);

inout [7:0] par_d; //双向端口
input ps_flag,
d_in,
rst,
clk;
output dout;

//定义参数与中间变量

parameter
s_2_p=1'b0,
p_2_s=1'b1;

reg par_en;
reg dout;
reg [2:0] counter;
reg [7:0] pd_reg;

assign par_d=par_en?pd_reg:8'hzz;

always@(posedge clk or negedge rst)
if(!rst)
begin
counter=3'b111;
par_en=0;
end
else
begin
if(ps_flag==s_2_p)
begin
  par_en=0;
  pd_reg[counter]=d_in;
  if(counter==3'b000)
   par_en=1;
  else;
  counter=counter-1;
end
else if(ps_flag==p_2_s)
begin
  dout=par_d[counter];
  counter=counter-1;
end
end

always@(ps_flag)
counter=3'b111;

endmodule