原创 modelsim simulation detail

Clock Generator:

use

always begin
  # (CLK_PERIOD/2) SYS_CLK <= ~SYS_CLK;
 end
     
 always begin
  # (DMTCLK_PERIOD/2) DVI_CLK <= ~DVI_CLK;
 end

NOT use

always begin
  # (CLK_PERIOD/2) SYS_CLK <= ~SYS_CLK;
  # (DMTCLK_PERIOD/2) DVI_CLK <= ~DVI_CLK;
 end

the second coding is not what you want!!!!

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DCM's RESET:

at least three cycle of DCM's CLKIN.

use

parameter RST_ACT_VAL = 5;
parameter CLK_PERIOD = 10;
#100;
RST = 1;
# (XRST_ACT_VAL * CLK_PERIOD);
RST = 0;

NOT use

#100;
RST = 1;
# 13.8;
RST = 0;