初次写博客，记录一下时光，一名大三的在校生........
一下午的仿真居然是时间period设置了错误。。。
贴一下仿真图
代码如下：
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: jiahua
//
// Create Date: 14:19:21 09/19/2014
// Design Name: sdram_test
// Module Name: sdram_init
// Project Name: sdram_control
// Target Devices: sprant6
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sdram_init(
sys_clk,
sys_rstn,
sdram_cmd,
sdram_addr,
//start_init,
done_signal
);
input sys_clk;
input sys_rstn;
//input start_init;
output done_signal;
output [4:0]sdram_cmd; // [4]CKE , [3]CSn, [2]RASn, [1]CASn, [0]WEn
output [13:0]sdram_addr; // [13:12]BA , [11:0]A
wire [4:0]sdram_cmd;
wire [13:0]sdram_addr;
/////////////////////////////////////////////////////////////////////////////////////
parameter mode_set_reg = 13'b00000_000_010_0_010;
//突发读写 lantency 2 连续读写 突发读写长度4
/////////////////////////////////////////////////////////////////////////////////////
//command
reg [4:0]command;
reg [13:0]sdram_add;
parameter pre_cmd = 5'b10010,
auto_cmd = 5'b10001,
nop = 5'b10111,
mode_cmd = 5'b10000;
/////////////////////////////////////////////////////////////////////////////////////
//T=10ns
parameter stable_200us = 15'd19999,
tRP_20ns = 2'b1,
tRFC_70ns = 3'd6,
tMRD_20ns = 2'b1;
reg [14:0]count;
reg count_start;
always @(posedge sys_clk)
begin
if(!sys_rstn)
count <= 15'd0;
else if(count >= stable_200us)
count <= 15'd0;
else if(count_start)
count <= count + 1'b1;
else
count <= 15'd0;
end
reg [5:0]state;
parameter power_on = 6'b000_001,
precharge = 6'b000_010,
autofresh1 = 6'b000_100,
autofresh2 = 6'b001_000,
mode_set = 6'b010_000,
idle = 6'b100_000;
reg init_done;
always @(posedge sys_clk)
begin
if(!sys_rstn)
begin
state <= power_on;
init_done <= 1'b0;
end
else
case(state)
power_on:
if(count == stable_200us)
begin
state <= precharge;
command <= pre_cmd;
//tRP_20ns <= 1'b1;
count_start <= 1'b0;
sdram_add[11] <= 1'b1;
end
else
begin
state <= power_on;
count_start <= 1'b1;
end
precharge:
if(count == tRP_20ns)
begin
state <= autofresh1;
command <= auto_cmd;
count_start <= 1'b0;
end
else
begin
state <= precharge;
command <= nop;
count_start <= 1'b1;
end
autofresh1:
if(count == tRFC_70ns)
begin
state <= autofresh2;
command <= auto_cmd;
count_start <= 1'b0;
end
else
begin
state <= autofresh1;
command <= nop;
count_start <= 1'b1;
end
autofresh2:
if(count == tRFC_70ns)
begin
count_start <= 1'b0;
state <= mode_set;
command <= mode_cmd;
sdram_add <= mode_set_reg;
end
else
begin
state <= autofresh2;
command <= nop;
count_start <= 1'b1;
end
mode_set:
if(count == tMRD_20ns)
begin
state <= idle;
command <= nop;
count_start <= 1'b0;
end
else
begin
state <= mode_set;
command <= nop;
count_start <= 1'b1;
end
idle:
begin
command <= nop;
init_done <= 1'b1;
end
default:
begin
state <= power_on;
init_done <= 1'b0;
end
endcase
end
assign sdram_cmd = command;
assign sdram_addr =sdram_add;
assign done_signal = init_done;
endmodule
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用户403664 2014-9-23 17:34