原创 【博客大赛】【原创】Verilog自制交通灯控制器加倒计时功能(内带源码文件)

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        无论是课程设计，还是实验课，最好的方法就是在FPGA实验板上进行测试实验，这样可以看到实际交通灯的效果。对每一部分修改可以看到修改的效果，知道程序的修改带来的效果，那样比只看代码要理解的更深刻。
     在设计中最好是分模块设计，状态控制，脉冲发生等部分，对每个模块的调试书写时要特别注意每位的意义，尤其在软件绑定引脚时，每个输入输出信号的绑定，引脚的输入输出特性等，要与实际代码中的相符，在调试中不断发现问题，解决问题。

下面附上代码部分：
 

自制交通灯控制器加倒计时功能：

module traffic(CLK,EN,LIGHT_A,LIGHT_B,TIME_A,TIME_B,a,b,c,d,e,f,g);

output[7:0] TIME_A,TIME_B;

output[2:0] LIGHT_A,LIGHT_B;

output[3:0] a,b,c,d,e,f,g;

input CLK,EN;

reg[7:0] numa,numb;

reg tempa,tempb;

reg[1:0] counta,countb;

reg[5:0] ared,ayellow,agreen,bred,byellow,bgreen;

reg[2:0] LIGHT_A,LIGHT_B;

reg[3:0] a,b,c,d,e,f,g;

always @(EN)

  if(!EN) 

    begin

      ared <=8'd45;

      ayellow <=8'd05;

      agreen <=8'd40;

      bred <=8'd45;

      byellow <=8'd05;

      bgreen <=8'd40;

    end

assign TIME_A=numa;

assign TIME_B=numb;

always @(posedge CLK)

   begin

      if(EN)

         begin

            if(!tempa)

                begin

                   tempa<=1;

                      case(counta)

                     0: begin numa<=ared; LIGHT_A<=4; counta<=1; end

                     1: begin numa<=agreen; LIGHT_A<=1; counta<=2; end

                     2:begin numa<=ayellow; LIGHT_A<=2;counta<=0; end

                      default: LIGHT_A<=4;

                      endcase

               end

           else

              begin

                if(numa>=1)

                if(numa[3:0]==0)

                   begin

                      numa[3:0]<=9;

                      numa[7:4]<=numa[7:4]-1;

                   end

                else numa[3:0]<=numa[3:0]-1;

               if (numa==0) tempa<=0;

              end

           end

        else

           begin

             LIGHT_A<=4;

             counta<=0;

             tempa<=0;

           end

    end

always @(posedge CLK)

   begin

      if (EN)

         begin

            if(!tempb)

                begin

                   tempb<=1;

                   case (countb)

                    0: begin numb<=bgreen; LIGHT_B<=1; countb<=1; end

                    1:begin numb<=byellow; LIGHT_B<=2; countb<=2; end

                    2: begin numb<=bred; LIGHT_B<=4; countb<=0; end

                      default: LIGHT_B<=1;

                   endcase

                end

            else

               begin

                 if(numb>=1)

                 if(!numb[3:0])

                     begin

                       numb[3:0]<=9;

                       numb[7:4]<=numb[7:4]-1;

                     end

                 else numb[3:0]<=numb[3:0]-1;

                if(numb==0) tempb<=0;

              end

           end

       else

          begin

             LIGHT_B<=4;

             tempb<=0;

             countb<=0;

          end

    end

always @(TIME_A)

begin

case(TIME_A[7:4])

4'd0:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b1111110;

4'd1:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b0110000;

4'd2:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b1101101;

4'd3:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b1111001;

4'd4:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b0110011;

4'd5:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b1011011;

4'd6:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b1011111;

4'd7:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b1110000;

4'd8:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b1111111;

4'd9:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'b1111011;

default:{a[3],b[3],c[3],d[3],e[3],f[3],g[3]}=7'bx;

endcase

end

always @(TIME_A)

begin

case(TIME_A[3:0])

4'd0:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b1111110;

4'd1:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b0110000;

4'd2:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b1101101;

4'd3:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b1111001;

4'd4:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b0110011;

4'd5:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b1011011;

4'd6:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b1011111;

4'd7:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b1110000;

4'd8:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b1111111;

4'd9:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'b1111011;

default:{a[2],b[2],c[2],d[2],e[2],f[2],g[2]}=7'bx;

endcase

end

always @(TIME_B)

begin

case(TIME_B[7:4])

4'd0:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b1111110;

4'd1:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b0110000;

4'd2:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b1101101;

4'd3:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b1111001;

4'd4:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b0110011;

4'd5:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b1011011;

4'd6:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b1011111;

4'd7:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b1110000;

4'd8:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b1111111;

4'd9:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'b1111011;

default:{a[1],b[1],c[1],d[1],e[1],f[1],g[1]}=7'bx;

endcase

end

always @(TIME_B)

begin

case(TIME_B[3:0])

4'd0:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b1111110;

4'd1:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b0110000;

4'd2:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b1101101;

4'd3:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b1111001;

4'd4:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b0110011;

4'd5:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b1011011;

4'd6:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b1011111;

4'd7:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b1110000;

4'd8:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b1111111;

4'd9:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'b1111011;

default:{a[0],b[0],c[0],d[0],e[0],f[0],g[0]}=7'bx;

endcase

end

endmodule