原创 基于VHDL的电子时钟设计（1）

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTC IS
   PORT(CLK,CLK0,R,BCD1WR,BCD10WR:IN STD_LOGIC;
        A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
        SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
   END COUNTC;
ARCHITECTURE ONE OF COUNTC IS
SIGNAL BCD1N:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL BCD10N:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
P1:PROCESS(CLK,BCD1WR)
   BEGIN
    IF R='1' THEN
     BCD1N<="0000";
    ELSIF BCD1WR='1' THEN
     BCD1N<=A;
    ELSIF CLK'EVENT AND CLK='1' THEN
       IF BCD1N="1001" THEN
          BCD1N<="0000";
       ELSE BCD1N<=BCD1N+1;
       END IF;
END IF;
END PROCESS P1;
P2:PROCESS(CLK,BCD10WR)
BEGIN
    IF R='1' THEN
     BCD10N<="000";
ELSIF BCD10WR='1' THEN
     BCD10N<=A(2 DOWNTO 0);
ELSIF CLK'EVENT AND CLK = '1' THEN
     IF(BCD1N = "1001") THEN
       IF BCD10N="101" THEN
          BCD10N<="000";
       ELSE BCD10N<=BCD10N+1;
       END IF;
     END IF;
   END IF;
END PROCESS P2;
P3:PROCESS(CLK0,BCD1N,BCD10N)
BEGIN
IF CLK0 = '1' THEN
SEL <= "001";
CASE BCD1N IS
WHEN "0000"=>Y<="0111111";
WHEN "0001"=>Y<="0000110";
WHEN "0010"=>Y<="1011011";
WHEN "0011"=>Y<="1001111";
WHEN "0100"=>Y<="1100110";
WHEN "0101"=>Y<="1101101";
WHEN "0110"=>Y<="1111101";
WHEN "0111"=>Y<="0000111";
WHEN "1000"=>Y<="1111111";
WHEN "1001"=>Y<="1101111";
WHEN "1010"=>Y<="1110111";
WHEN "1011"=>Y<="1111100";
WHEN "1100"=>Y<="0111001";
WHEN "1101"=>Y<="1011110";
WHEN "1110"=>Y<="1111001";
WHEN "1111"=>Y<="1110001";
WHEN OTHERS => NULL;
END CASE;
ELSE SEL <="010";
CASE BCD10N IS
WHEN "000"=>Y<="0111111";
WHEN "001"=>Y<="0000110";
WHEN "010"=>Y<="1011011";
WHEN "011"=>Y<="1001111";
WHEN "100"=>Y<="1100110";
WHEN "101"=>Y<="1101101";
WHEN "110"=>Y<="1111101";
WHEN "111"=>Y<="0000111";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS P3;
END ONE;