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module div_3(dout,clk_ser);
input clk_ser;
output dout;
reg[1:0] flag_a;
reg[1:0] flag_b;
reg div_a;
reg div_b;
wire div_3;
reg[3:0] count;
reg div_reg;
assign div_3=div_a^(div_a&div_b); //div_3即为三分频信号
assign dout=(count==4'b0000)?div_reg:0; //三分频作为同步信号，定时输出
always @(posedge div_3)
begin
count<=count+1;
div_reg<=div_3;
end
always @(posedge clk_ser)
begin
if(flag_a==2'b00)
begin
div_a<=0;
flag_a<=flag_a+1;
end
else if(flag_a==2'b01)
begin
div_a<=1;
flag_a<=flag_a+1;
end
else if(flag_a==2'b10)
begin
div_a<=1;
flag_a<=2'b00;
end
end
always @(negedge clk_ser)
begin
if(flag_b==2'b00)
begin
div_b<=1;
flag_b<=flag_b+1;
end
else if(flag_b==2'b01)
begin
div_b<=0;
flag_b<=flag_b+1;
end
else if(flag_b==2'b10)
begin
div_b<=0;
flag_b<=2'b00;
end
end
endmodule
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