原创 DE1实践之VGA显示（8bit色彩）

理解了VGA显示的原理，其实就是一个时序的驱动而已，比以前玩单片机驱动1602还要轻松很多。因为DE1开发板的RGB并不是三个数字输入，而是12个，其外围电路用了电阻分压，是得到的色彩更细，精度更高。但次试验中，我只是把他当做简单的三位，所以看到后面的代码有rgb_r0，rgb_r1，rgb_r2，rgb_r3一起出现，其实本质就是一个。

另外注意编写verilog代码时wire和reg的区别，一般默认的数据类型都是wire，所以赋值时只能用assign，如果是reg型，则可以直接赋值。另外在always和initial语句中只能用reg型（两者的区别我暂时只能体会到这里，估计还没有体会到其本质的区别，呵呵）。

verilog代码如下：

module VGA_8(

        clk50,reset,hsync,vsync,

        rgb_r0,rgb_r1,rgb_r2,rgb_r3,

        rgb_g0,rgb_g1,rgb_g2,rgb_g3,

        rgb_b0,rgb_b1,rgb_b2,rgb_b3

        );                  //the defination of the VGA_8 module

input clk50,reset;

output hsync,vsync;

output rgb_r0,rgb_r1,rgb_r2,rgb_r3;

output rgb_g0,rgb_g1,rgb_g2,rgb_g3;

output rgb_b0,rgb_b1,rgb_b2,rgb_b3;

reg[10:0] hcount;

reg[9:0]vcount;

reg hsync,vsync;

wire valid;

wire[10:0] x_point,y_point;

wire block1,block2,block3,block4,block5,block6,block7,block8;

//    method 1:

always@(posedge clk50 or negedge reset)

begin

    if(!reset)

    begin

         hcount<=11'd0;

         vcount<=10'd0;

    end

    else

    begin

        if(hcount==1040)

        begin

             hcount<=11'd0;

             vcount<=vcount+1;

        end

        else

             hcount<=hcount+1;

        if(vcount==666)

            vcount<=10'd0;

    end

end

/*

//  method 2:

always@(posedge clk50 or negedge reset)      //x count

begin

    if(!reset)hcount<=11'd0;

    else if(hcount==1040)hcount<=11'd0;

    else  hcount<=hcount+1;

end

always@(posedge clk50 or negedge reset)      //y count

begin

    if(!reset)vcount<=11'd0;

    else if(vcount==666)vcount<=10'd0;

    else if(hcount==1040) vcount<=vcount+1;

end

*/

always@(posedge clk50 or negedge reset)      //generate the signal hsync

begin

    if(!reset)hsync<=1'd1;

    else if(hcount==0)hsync<=1'd0;

    else if(hcount==120)hsync<=1'd1;

end

always@(posedge clk50 or negedge reset)      //generate the signal vsync

begin

    if(!reset)vsync<=1'd1;

    else if(vcount==0)vsync<=1'd0;

    else if(vcount==6)vsync<=1'd1;

end

assign valid=(hcount>=11'd176)&&(hcount<=11'd976)&&(vcount>=10'd43)&&(vcount<=10'd643);   //the valid display area

assign x_point=hcount-11'd176;                                         //the real x point

assign y_point=vcount-10'd43; 

                                       //the real y point

assign block1=(x_point>=0)&&(x_point<100);                               //generate the different area

assign block2=(x_point>=100)&&(x_point<200);

assign block3=(x_point>=200)&&(x_point<300);

assign block4=(x_point>=300)&&(x_point<500);

assign block5=(x_point>=400)&&(x_point<500);

assign block6=(x_point>=500)&&(x_point<600);

assign block7=(x_point>=600)&&(x_point<700);

assign block8=(x_point>=700)&&(x_point<800);

assign   rgb_r0=valid?(block1|block5|block7|block8):1'd0;      //digital RGB

assign   rgb_r1=valid?(block1|block5|block7|block8):1'd0;

assign   rgb_r2=valid?(block1|block5|block7|block8):1'd0;

assign   rgb_r3=valid?(block1|block5|block7|block8):1'd0;

assign   rgb_g0=valid?(block2|block3|block5|block7):1'd0;

assign   rgb_g1=valid?(block2|block3|block5|block7):1'd0;

assign   rgb_g2=valid?(block2|block3|block5|block7):1'd0;

assign   rgb_g3=valid?(block2|block3|block5|block7):1'd0;

assign   rgb_b0=valid?(block2|block5|block6|block8):1'd0;

assign   rgb_b1=valid?(block2|block5|block6|block8):1'd0;

assign   rgb_b2=valid?(block2|block5|block6|block8):1'd0;

assign   rgb_b3=valid?(block2|block5|block6|block8):1'd0;

endmodule