原创 交通管理器设计

综合训练-交通管理器设计<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

题目：甲、乙道路交替通行，每次通行时间30s，交替通行时刻，要求有5s的准备时间，即每次绿灯变红灯时，黄灯应先亮5s。而红灯变绿灯则不需要亮黄灯

文本代码

顶层代码

module top(clk,rst,R1,R2,G1,G2,Y1,Y2);

input clk,rst;

output R1,R2,G1,G2,Y1,Y2;

wire FIN25,FIN5,EN25,EN5;

controller m1(clk,rst,EN25,EN5,FIN25,FIN5,R1,R2,G1,G2,Y1,Y2);

time25 m2(clk,rst,EN25,FIN25);

time5 m3(clk,rst,EN5,FIN5);

endmodule

控制代码

module controller(clk,rst,EN25,EN5,FIN25,FIN5,R1,R2,G1,G2,Y1,Y2);

input clk,rst,FIN25,FIN5;

output EN25,EN5,R1,R2,G1,G2,Y1,Y2;

reg EN25,EN5,R1,R2,G1,G2,Y1,Y2;

reg[1:0]state;

parameter S0=0,S1=1,S2=2,S3=3;

always @(posedge clk)

  begin

       if(!rst)begin

                     R1=0;Y1=0;G1=0;R2=0;Y2=0;G2=0;

                     EN25=0;EN5=0;state=0;

                     end

    else begin

               case(state)

                S0:begin

                       R1=0;Y1=1;G1=1;R2=1;Y2=1;G2=0;

                       EN25=1;EN5=0;

                       if(FIN25==1) state="S1";

                      end

                S1:begin

                        R1=0;Y1=1;G1=1;R2=1;Y2=0;G2=1;

                        EN25=0;EN5=1;

                        if(FIN5==1) state="S2";

                      end

                S2:begin

                        R1=1;Y1=1;G1=0;R2=0;Y2=1;G2=1;

                        EN25=1;EN5=0;

                        if(FIN25==1) state="S3";

                      end

                S3:begin

                        R1=1;Y1=0;G1=1;R2=0;Y2=1;G2=1;

                        EN25=0;EN5=1;

                        if(FIN5==1) state="S0";

                      end

               endcase

              end

  end

endmodul

定时计数代码

//25s定时

module time25(clk,rst,EN25,FIN25);

input clk,rst,EN25;

output FIN25;

reg FIN25;

reg[40:0]count;

always@(posedge clk)

  begin

       if(!rst) begin

                            count=0;FIN25=0;

                      end

       else if(EN25) begin

                                   count=count+1;

                                   if(count==50)

                                          FIN25=1;

                              end

          else begin

                     count=0;

                     FIN25=0;

                    end

  end

endmodule

//5s定时

module time5(clk,rst,EN5,FIN5);

input clk,rst,EN5;

output FIN5;

reg FIN5;

reg[40:0]count;

always@(posedge clk)

  begin

       if(!rst) begin

                            count=0;FIN5=0;

                      end

       else if(EN5) begin

                                   count=count+1;

                                   if(count==10)

                                          FIN5=1;

                                          end

                                   else begin

                                                 count=0;

                                                 FIN5=0;

                                          end

  end

endmodule