原创 Despite Intel's chips on the table, EUV still not a sure success

Proponents of extreme ultraviolet (EUV) lithography were reasonably encouraged a few weeks ago when Intel Corp. entered into a $4.1 billion equity and funding deal to help boost R&D efforts for 450-mm and EUV lithography tools.

"It's the best news I've heard in a long time," said David Brandt, senior director of euv marketing and business development at Cymer Inc., a long-time source developer for ASML and the front-runner in working with the Dutch lithography vendor to improve source power for EUV tools.

Intel already had a vested stake in making sure that EUV development remains on track to put the technology into production, even if much later than Intel had originally hoped. Intel and the rest of the thinning ranks of leading-edge chip makers have every reason to want cost-effective EUV lithography to save them from the pain and expense of extending 193-nm optical lithography to the 10-nm node and beyond. Brandt and others took Intel's willingness to put skin in the EUV game as a vote of confidence in the viability of the oft-delayed technology.

But Intel's wallet alone won't bring EUV into production. Though incremental progress on the EUV development front has been reported over the past week, there remains—as there has since the technology landed on the ITRS roadmap—work to be done. EUV is, at best, still years away from volume production and remains no slam dunk.

In a presentation at last week's Semicon West tradeshow, Franklin Kalk, chief technology officer at Toppan Photomasks Inc., said source power, mask defectivity and photoresist performance remain the three issues still facing volume production of chips using EUV. But, Kalk said, source power remains the main hurdle, as it has for some time.

Three years ago, Kalk said, mask defectivity was considered the main stumbling block for EUV, and thus the burden of Toppan and its competitors. But in the past couple of years, the failure to develop a source powerful and reliable enough to provide adequate tool throughput has taken centre stage. "I'm hoping that source power gets high enough that they start complaining about the masks again."

Chip makers want EUV tools with a throughput of 100 to 150 wafers per hour to make production EUV cost effective. Some say a tool throughput of 60 to 80 wafers per hour would be a sufficient starting point. Even that type of throughput remains out of reach for now, though AMSL CEO Eric Meurice said this week that research progress indicates that EUV throughput is on pace to reach 70 wafers per hour in 2014 and 125 wafers per hour in 2016.

More incremental progress
Other EUV progress has also been reported in the previous weeks:
On source power: Nigel Farrar, vice president of technical marketing at Cymer, said Cymer has now achieved about 50 watt expose power on its HVM I source using a pre-pulse—which conditions the target prior to the main pulse—at full repetition rate using closed loop controls. (Back in February, Cymer also reported average power of 50 watts, but that was in open loop testing, minus the power-reducing controls placed on systems in the field to improve stability.)

Meurice said the potential for 105 watts has been confirmed in lab experiments, supporting ASML's roadmap to volume production starting at 70 wafers per hour in 2014 and upgradable to 125 wafers per hour in 2016. He cautioned that in-situ experiments, as opposed to lab experiments, are still necessary to confirm this roadmap. Even if ASML stopped development now, Meurice said the lab data demonstrated that ASML's NXE:3300—the production tool successor to the pre-production NXE 3100 systems installed at several customer sites—would support throughput of 30 to 40 wafers per hour based on its superior architecture and energy efficiency. (Halting development, of course, is not the plan).

Source availability: Farrar said Cymer's HVM I sources have been running at about 70 per cent availability for the past two quarters, up from 50 per cent in prior quarters. Only about 10 per cent of the downtime was unscheduled, the rest was for planned maintenance.

Source collector durability: Cymer has demonstrated stable reflectivity for its EUV source collector over more than 30 billion pulses. Collector reflectivity is a key issue because replacing the collector is a major undertaking and the collector's performance will degrade over time. Cymer does not know how long the source can last between replacements, but 30 billion pulses over more than a year is considered encouraging.

Mask defectivity: Kalk acknowledged that EUV masks will not be defect-free. Due to the complexity involved, every EUV mask blank will have defects, an multi-layer mask blank defects cannot be repaired, Kalk said. But masks must be "defect free enough" to work, he said. In the case of memory, design patterns are redundant enough that the mask can be shifted and rotated accordingly in order to write the pattern around the defects—if mask makers know where they are, according to Kalk. Improvement in both blank and mask inspection tools, as well as mask writer accuracy, is required, Kalk said.

Mask durability: No one will know exactly how long an EUV mask will last until they are used in high volume production. Kalk said different mask durability issues—including the appearance of haze on a mask and, later, mask absorber degratdation—arose in the first six years or so after the introduction of 193-nm lithography, depending on the number of exposures for a mask. "We are going to encounter issues," Kalk said. 'I don't even know what they are yet, but we are going to encounter them."

Tools needed: The full tool kit for EUV masks won't be ready until about 2018, according to Kalk. He said development is needed on blank and mask inspection tools, as well as the Carl Zeiss EUV actinic aerial image metrology system (AIMS) for reticle defect and printability analysis. Kalk said that EUV insertion can occur before the full mask tool kit is in place, but that a "bridge strategy" will be required. As manufacturing eventually ramps up, new issues will arise he said.