原创 System Verilog : Functional Coverage Guidelines

We have been implementing every possible checks to make sure design is verified but what have we done to check our test bench ? How do we make sure that our test bench has covered everything that needs to be covered w.r.t to specification and test plans ? Here is the place “Functional Coverage” and “SVA” comes in picture!

Before we start on few guidelines to follow while working with functional coverage, I would encourage you to refer various posts on functional coverage and assertions to get high level idea on architecture and usage. Click on below links

1. http://asicwithankit.blogspot.in/2011/01/coverage-model-in-system-verilog-test.html

2. http://www.asicwithankit.blogspot.com/2012/12/system-verilog-functional-coverage.html

3. http://www.asicwithankit.blogspot.com/2013/01/the-two-door-keepers-assertion-to-make.html
 

To conclude with few guidelines from various posts on functional coverage and assertions:

Functional coverage and code coverage both are contributing highly on sign off criteria for verification. Verification engineers have to make sure that their test plan and test environment is intelligent enough to satisfy the code/functional coverage closer. Code coverage is generated by tool with the help of the simulations generated by the test environment. So test environment should be random and intelligent enough to make sure design is covered as a part of code coverage and designer should be in agreement while code coverage review. There should be valid comments with reason for all exclusions for code coverage w.r.t to design specification. Functional coverage should be written such a way that it should be able to capture all identified functionality while defining the test plan. Coverage and assertions are very important entity in the verification process and there are few guidelines that would help in verification process.

Few guidelines while working with functional coverage
 

1. Your test plan should be based on the functionality you want to verify w.r.t to specification
2. You should have a coverage matrix with the list of cover point details w.r.t to your test plan scenario and there should be link of traceability between test scenario and cover point.
3. Environment should have control mechanism for enabling or disabling coverage and assertions for better control ability in your environment
4. Don’t enable functional coverage at the beginning of the verification to avoid simulation overhead in the starting phase of verification
5. During the initial time of the verification bug ration is typically high, as you move forward to the verification bug ration would start to drop. Here is the time when you should enable coverage and analyze it
6. Functional coverage plan needs to be updated as verification progresses
7. As your knowledge of the design and corner case understanding increases, you should keep updating your functional coverage plan
8. Make effective use of cover group “trigger” and sampling mechanism. (Stay tune for sampling mechanism on upcoming blog post !)
9. Follow meaningful names of cover group and cover points. This will help when you in debug process
10. Coverage should not be captured on failing simulations. Make sure to gathered coverage for only passing simulation. If few tests are not passing in regression first make sure to fix those issues before come to a conclusion on coverage achievement
11. If your tests are keep exercising the same logic in design, start developing the new tests for uncovered coverage part of coverage (coverage holes)

For guidelines on SVA, please refer to this article (http://www.asicwithankit.blogspot.com/2014/08/system-verilog-assertions-sva-types.html) !

Stay tuned to understand functional coverage sampling mechanism !

Thanks,
ASIC With Ankit