原创 错误1

2013-8-21 19:16 470 2 2 分类: FPGA/CPLD
仿真时,值赋不上。s_2,什么的都是高阻态
 always @(posedge clk or negedge rst_n)
    if( !rst_n )begin
b_1<=32'd0;
a_1<=32'd0;
c_i1<=1'b0;
 
b_2<=32'd0;
a_2<=32'd0;
c_i2<=1'b0;
s_o<=32'h28333;
 preprData[79:0]<=80'd0;end
else case (i)
 
4'd0:  if (ONE_Done_Sig_pos)
          i<=i+1'b1;
          
 
      4'd1: begin b_2<=rData[32:0];
 a_2<=s_o; 
 i<=i+1'b1;end
 
 
  4'd2:    begin preprData[31:0]<=s_2;
         preprData[79:32]<=rData[79:32];
i<=i+1'b0;end
      
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