原创 verilog学习笔记【4位全加器】

程序

module adder(ina,inb,cin,sum,cout);
    input [3:0] ina,inb;
    input cin;
    output [3:0] sum;
    output cout;
   
    assign {cout,sum} = ina + inb + cin;
endmodule

测试程序

`timescale 1ns/1ns
module adder_tb();
    reg [3:0] ina,inb;
    reg cin;
    wire [3:0] sum;
    wire cout;
    adder ad(ina,inb,cin,sum,cout);
   
    initial
    begin
        #20
        ina = 4'b0001;
        inb = 4'b0001;
        cin = 1'b1;
        #20
        ina = 4'b0000;
        inb = 4'b0000;
        cin = 1'b0;
        #20
        ina = 4'b1111;
        inb = 4'b1111;
        cin = 1'b0;
    end
endmodule