原创 verilog学习笔记【译码器】

程序
module decoder3_8(in,en,out);
    input [2:0] in;
    input en;
    output [7:0] out;
   
    reg [7:0] out;
    always@(in,en)
    begin
        if(!en)
        out = 8'b0;
        else
        case(in)
            3'b000:out = 8'b_0000_0001;
            3'b001:out = 8'b_0000_0010;
            3'b010:out = 8'b_0000_0100;
            3'b011:out = 8'b_0000_1000;
            3'b100:out = 8'b_0001_0000;
            3'b101:out = 8'b_0010_0000;
            3'b110:out = 8'b_0100_0000;
            3'b111:out = 8'b_1000_0000;
            default:out = 8'b_0000_0000;
            endcase
    end
endmodule

测试程序
`timescale 1ns/1ns
module decoder3_8tb();
reg [2:0] in;
reg en;
wire [7:0] out;
decoder3_8 decoder(in,en,out);

initial
begin
    en = 0;
    #10
    en = 1;
    #10
    in = 3'b000;
    #10
    in = 3'b001;
    #10
    in = 3'b010;
    #10
    in = 3'b011;
    #10
    in = 3'b100;
    #10
    in = 3'b101;
    #10
    in = 3'b110;
    #10
    in = 3'b111;
end
endmodule