原创 占空比为50%的Verilog分频

当N为偶数时，1/N分频比较简单，计数到N/2 -1即可。

例如1/20分频：

module twenty_clk(reset,clk_in,clk_out);
output clk_out;
input reset,clk_in;
reg clk_out;
reg[3:0]j;

always @(posedge clk_in)
   if(!reset)
     begin
       clk_out<=0;
       j<=0;
     end
   else
     begin
        if(j==10)
           begin
               j<=0;
               clk_out<=~clk_out;
           end
        else
            begin
               j<=j+1;
               clk_out<=clk_out;
            end
    end
endmodule

当N为奇数的时候就麻烦一点，分别对时钟的上升沿和下降沿进行0到N-1的技术，在(N-1)/2  和N-1翻转，最后将两个结果或一下就可以了。

例如1/3分频：

module three_clk(reset,clk_in,clk_out);
output clk_out;
input reset,clk_in;
reg clk_out;
reg[1:0]i,j;
reg clk_out1,clk_out2;

always @(posedge clk_in)
   if(!reset)
     begin
       clk_out1<=0;
       j<=0;
     end
   else
     begin
        if(j==2)
           begin
               j<=0;
               clk_out1<=~clk_out1;
           end
        else if(j==1)
            begin
                j<=j+1;
               clk_out1<=~clk_out1;
            end
         else
            begin
               j<=j+1;
               clk_out1<=clk_out1;
            end
     end
   
  always @(negedge clk_in)
     if(!reset)
       begin
         clk_out2<=0;
         i<=0;
       end
     else
       begin
          if(i==2)
             begin
                 i<=0;
                 clk_out2<=~clk_out2;
             end
          else if(j==1)
              begin
                  i<=i+1;
                 clk_out2<=~clk_out2;
              end
           else
              begin
                 i<=i+1;
                 clk_out2<=clk_out2;
              end
       end

always @(clk_out1 or clk_out2) 
    clk_out=clk_out1 | clk_out2;

endmodule