Verification of USB Software Stack in a Development System using slower than standard clock timing (USB Slow Clock Option) T E C H N I C A L B R I E F Verification of USB Software Stack in a Development System (USB Slow Clock Option) Matthew Dunn LeCroy PSG Introduction Depending on the type of traffic being generated (High, Full, Low) we can divide the When developing a USB software stack which development system’s bit clock into the is to be embedded in an FPGA or ASIC, it is ……