DDR2与DDR3信号完整性及PCB设计Signal Integrity and PCB layout considerations for DDR2-800 Mb/s and DDR3 Memories Fidus Systems Inc. 900, Morrison Drive, Ottawa, Ontario, K2H 8K7, Canada Chris Brennan, Cristian Tudor, Eric Schroeter, Heike Wunschmann, and Syed Bokhari Session # 8.13 Abstract The paper addresses the challenge of meeting Signal Integrity (SI) and Power Integrity (PI) requirements of Printed Circuit Boards (PCBs) containing Double Data Rate 2 (DDR2) memories. The emphasis is on low layer count PCBs, typically 4-6 layers using conventional technology. Some design guidelines have been provided. 1. Introduction DDR2 usage is common today with a push towards higher speeds such as 800 Mbps [1] and more recently, 1066 Mbps. DDR3 [2] targets a data rate of 1600 Mbps. From a PCB implementation standpoint, a pri……