2006_ESD failure mechanisms of analog I_O cells in 0[1]102 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 6, NO. 1, MARCH 2006 ESD Failure Mechanisms of Analog I/O Cells in 0.18-m CMOS Technology Ming-Dou Ker, Senior Member, IEEE, Shih-Hung Chen, and Che-Hao Chuang Abstract―Different electrostatic discharge (ESD) protection schemes have been investigated to nd the optimal ESD protection design for an analog input/output (I/O) buffer in 0.18-m 1.8- and 3.3-V CMOS technology. Three power-rail ESD clamp devices were used in power-rail ESD clamp circuits to compare the protection efciency in analog I/O applications, namely: 1) gate-driven NMOS; 2) substrate-triggered eld-oxide device, and 3) substrate-triggered NMOS with dummy gate. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp cir……