A 155-MHz clock recovery delay and phase locked loopA 155-MHz Clock Recovery Delay- and Phase-Locked Loop Thomas H. Lee, Member, IEEE, and John F . Bulzacchelli, Student Member, IEEE Abstract-This paper describes a completely monolithic delay-locked loop (DLL) that may be used either by itself as a deskewing element, or in conjunction with an external voltagecontrolled crystal oscillator (VCXO) to form a delay- and phaselocked loop (DlPLL). By phase shifting the input data rather than the clock, the DLL and DlPLL provide jitter-peaking-free clock recovery. Additionally, the jitter transfer function of the DlPLL has a low bandwidth for good jitter filtering without compromising acquisition speed. The DlPLL described here exhibits less than 1" rms jitter on the recovered clock, independent of the input data density. No jitter peaking is obse……