u00780632A LOW-POWER CMOS FREQUENCY SYNTHESIZER DESIGN METHODOLOGY FOR WIRELESS APPLICATIONS Amr M. Fahim and Mohamed I. Elmasry Electrical & Computer Engineering Dept., University of Waterloo, Waterloo, CANADA ABSTRACT A new methodology is developed to allow design space exploration of CMOS frequency synthesizers (FS) for wireless applications. This methodology allows the comparison of different phase locked loop (PLL) and direct digital synthesizer (DDFS) architectures in terms of their spectral purity and power dissipation. An optimization strategy in which both the lock time and the phase noise are constrained while minimizing power dissipation has been constructed. The first order performance models used for this methodology have been verified to be accurate up to 5% of HPSICE simulations. Us……