modelsim教程 準備事項 1. ModelSim試用版下載 2. 範例程式下載 (史丹佛大學一門課的期末專題Implememtation of Viterbi Decoder：constrain length K=3, code rate R=1/2, register-exchange) 整個project共含7個Verilog程式：system.v (top-level)                                                        |-- clkgen.v                                                        |-- chip_core.v                                                                 |-- controller.v                                                                 |-- spu.v                                                                 |-- acs4.v                                                                        |-- acs1.v (或是另外一個Verilog的簡單例子，可以從C:\ SynaptiCAD\ Examples\ TutorialFiles\                                                                      VeriLoggerBasicVerilo……