Berrydale_Schematics_0p85 4 3 2 1 Berrydale- Daughter Card for Mainstone Evaluation Platform Sheet D Intel Confidential Description Cover Sheet Block Diagram Bulverde Flash SDRAM Marathon Marathon Crystal Local Memory LAI MicroDIMM LCD1 LCD2/LCD3 LCD/GIB LAI System Bus LAI Tranceivers Mainboard Connector Reset / Straps JTAG / UART CPLD System Bus Resistors FPGA Switch / LEDs Ethernet 1/2 USB AC'97 Power Delivery Chip Select / Interrupt Map Default Stuffing Option Rev History 4 3 2 D C B A 1 2 3-5 6 7 8-10 11 12 13 14-15 16 17 18 19-20 21-22 23 24 25 26 27-28 29 30-31 32 33 34-36 37 38 39 5 C B A Title Size B Date: Berrydale Daughter Card Document Number Tuesday, December 16, 2003 Sheet 1 R ev 4.2 1 of 39 5 4 3 2 1 Block Diagram Marathon Clocks Sheet 11 Intel Confidential D Bulverd……