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ExamplesofVHDLDescriptions
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时间:2019-12-20
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Combinationa Logic Exclusive-OR Gate (Dataflow style) Exclusive-OR Gate (Behavioura style) Exclusive-OR Gate (Structura style) Miscel aneous Logic Gates Three-input Majority Voter Magnitude Comparator Quad 2-input Nand (74x00) BCD to Seven Segment Decoder Dua 2-to-4 Decoder Octa Bus Transceiver Quad 2-input OR 8-bit Identity Comparator Hamming Encoder Hamming Decoder 2-to-4 Decoder with Testbench and Configuration Multiplexer 16-to-4 using Selected Signa Assignment Statement Multiplexer 16-to-4 using Conditiona Signa Assignment Statement Multiplexer 16-to-4 using if-then-elsif-else Statement M68008 Address Decoder Highest Priority Encoder N-input AND GateCounters Counter using a Conversion Function Generated Binary Up Counter Counter using Multiple Wait Statements Synchronous Down Counter with Paralle Load Mod-16 Counter using JK Flip-flops Pseudo Random Bit Sequence Generator Universa Counter/Register n-Bit Synchronous CounterShift Registers Universa Shift Register/Counter TTL164 Shift Register Behavioura description of an 8-bit Shift Register Structura Description of an 8-bit Shift RegisterMemory Classic 2-Process State Machine and Test Bench State Machine using Variable State Machine with Asynchronous Reset Pattern Detector FSM with Test Bench State Machine with Moore and Mealy outputs Moore State Machine with Explicit State encoding Mealy State Machine with Registered Outputs Moore State Machine with Concurrent Output LogicROM-based Waveform Generator A First-in First-out Memory Behavioura mode of a 16-word, 8-bit Random Access Memory Behavioura mode of a 256-word, 8-bit Read Only Memory State MachinesClassic 2-Process State Machine and Test Bench State Machine using Variable State Machine with Asynchronous Reset Pattern Detector FSM with Test Bench State Machine with Moore and Mealy outputs Moore State Machine with Explicit State encoding Mealy State Machine with Registered Outputs Moore State Machine with Concurrent Output LogicRegisters Universa Register Octa D-Type Register with 3-State Outputs Quad D-Type Flip-flop 8-bit Register with Synchronous Load and ClearSystems Pelican Crossing Controller Simple Microprocessor System Booth Multiplier Lottery Number Generator Digita Delay Unit Chess ClockADC and DAC Package defining a Basic Analogue type 16-bit Analogue to Digita Converter 16-bit Digita to Analogue Converter 8-bit Analogue to Digita Converter 8-bit Unipolar Successive Approximation ADCArithmetic 8-bit Unsigned Multiplier n-bit Adder using the Generate Statement A Variety of Adder Styles Booth Multiplier……
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