摘要： 随着集成电路 （Ic） 加快速度，上升/下降时代的大多数脉冲和函数生成器 （典型 5ns） 成为测量低于 20ns 的时间间隔不足。你可以克服这种限制与模拟交换机或先进的 CMOS 逻辑门，创建数字边速度更快。开通 / 这些开关关断时间产生非常快速上升/下降时间。单刀双掷 （SPDT） 开关，可以创建脉冲的高和低层次的是可编程。Maxim > App Notes > SIGNAL GENERATION CIRCUITS SWITCHES AND MULTIPLEXERS
Keywords: pulse generator, CMOS switches, CMOS logic gates, SPDT switch, analog switches, high speed pulse Jan 31, 2003
generator, MAX4644, fast rise/fall times, pull-up/pull down driver, SPDT analog switch, output driver, function
generators, fast digital edge
APPLICATION NOTE 1866
High-Speed Pulse Generator Has Programmable Levels
Abstract: As integrated circuits (ICs) speed up, the rise/fall times of most pulse and function generators (5ns
typical) become inadequate for measuring time intervals below 20ns. You can overcome this limitation with
analog switches or advanced CMOS logic gates, which create faster digital edges. The turn-on/ turn-off times
for these switches produce very fast rise/fall……
