标签: wafer

同文转自微信公众号“ESDiS Release”。每间wafer fab都存在的静电问题。 The electrostatics problems in the front-end manufacturing of semiconductors (ie. wafer fabrication) is quite different from those cases in back-end semiconductor manufacturing (ie. Chip assembly and testing), SMT and other common electronic manufacturing industries. Among the electrostatics problems, the electrostatics induced electrical failures of microelectronic devices is the typical representative case, ie. wafer top electrostatics damage mode. Figure1. the modes of wafer top electrostatics induced failures Such wafer top electrostatics failure mode exists in many processes, including the vacuum processes of PECVD (PID, Plasma process Induced Damage), Dry-etcher (PID), Asher (PID) and atmosphere processes of HPW (Highly Purified Water) rinsing cleaning, Spin dryer after rining cleaning, scrubber cleaning with spinning, etc. Figure2. a typical HPW rinsing cleaner with spinning Eventually, the back-end manufacturing of semiconductors (Chip Assembly and Testing) also exist such wafer top electrostatics induced damage and the process is also the rinsing cleaning at wafer sawing process. However, due to the big differences of wafer interior circuits, the production yield failure problem caused bysuch wafer top electrostatics is much more sensitive and severer in wafer Fabs than chip assembly and testing production lines. Figure3. PID problem in a dry etcher of wafer Fabs The Wafer top electrostatics induced damage mode is also highly related with wafer internal circuit layout and process technology scaling levels. Among nowadays mainstream semiconductor products, more and more fall into the scope of65nm technology process and below. Typically, the sensitivity level of such wafer top electrostatics induced failures at wafer fabs most goes to below 100 volts and even only several volts for the most advanced semiconductors.

It had been a while since I visited India for biz and my recent trip to Bangalore for the Indian Electronics Semiconductor Association (IESA) Vision Summit 2015 early this month was an eye opener on the vast potential the country holds as an economic power. All of us are aware of the euphoria building up with the new Prime Minister and his forward-looking pro-business policies. Countries including US, Japan, Australia and others have been pledging very high amount of business interests into India. The Make in India mantra to transform the country from a consumer state to a manufacturing one has been gaining a huge amount of momentum. A big focus here is the resurfacing of semiconductor wafer fab manufacturing initiative and what better opportunity than this could be for the mature semiconductor manufacturing industry ecosystem in Singapore to take advantage of and look for significantly large business opportunities. A significantly high profile event, the Vision Summit attracted 600+ delegates. I had the opportunity to share the stage with some eminent industry leaders who shared their insights on this high value manufacturing. The panel discussion, "Semiconductor Fab – The Opportunity, Challenges Accelerators" was quite lively and interesting. The place was abuzz with activities and I list below a few of my takeaways on the Indian semiconductor happenings. Focus on Semiconductor Fabs in India Long been a missing key entity in the Indian semiconductor eco-system, this has got a renewed focus from the Government of India, especially courtesy the alarmingly increasing trade deficit gap for electronic products and components in the country. Most of the demand from the huge electronics growth – fuelled by increasing purchasing power of a large domestic market—is presently being met through imports. With the present domestic electronics production and services still lagging behind and the demand projected to rise, this gap is expected to widen further. In fact, India’s electronic goods and component import bill is expected to far exceed its oil import bill at this rate. The government is paying attention and fast tracking these initiatives/activities to avoid a future crisis due to this deficit gap. Last year, the Indian government gave the go-ahead for 2 semiconductor consortia to set up fabs in the country. One consortium includes Jaiprakash Associates, Tower Semiconductor and IBM and the other includes HSMC Technologies, Silterra and STMicroelectronics. The sites for the two proposed fabs (one from each consortium) have already been identified – the former in the state of Chattisgarh and the latter in Gujarat. The setting up of the fabs will open up huge opportunities for ancillary industries too – besides the fab infrastructure, equipment and material vendors etc. Expect to have the ecosystem quickly developing around these fabs once the ground-breaking starts. Singapore with its mature semiconductor manufacturing eco-system has much to offer here. Companies in   Singapore have evinced keen interest and are awaiting some clear signals on the fabs’ start-up timeline and status. States wooing businesses and investments A pleasant surprise for me personally was to see the "men in power" aka state government officials actively wooing for businesses and investments in their states – a 180-degree turnaround from the earlier days! The "Make in India" focus from the Indian government includes several growth and industry conducive policies and incentives as it aims to transform India from a consumption driven market to one with manufacturing capability. Several state governments were present and actively pitching for their states. MoUs and White Paper A few MoUs were signed signalling collaboration between industry- academia as well as across industry associations between countries. IESA and SSIA (Singapore Semiconductor Industry Association) signed a MoU agreeing to establish and develop trade and technical cooperation links between the electronics and semiconductor manufacturers of both countries in general and their respective members in particular. IESA and SSIA also jointly released a White Paper on India Singapore ESDM (Electronics Systems Design and Manufacturing) industry collaboration opportunities—the latter is something that I had also worked on, on behalf of SSIA. Strong presence of Small and Micro-small business entities This is a rapidly increasing sector and denotes a strong entrepreneur mind-set. This includes people previously having worked in MNCs and starting up something in a niche, returning Non-resident Indians eager to leverage on the Make in India focus, traditional family run businesses entering the services sector in this space and a sizeable number of experience rich freelance consultants. The government has also come up with initiatives to address this important and, if I may add, "neglected but vital" segment. Keynotes, Panel discussions, Press briefings Quite a few insightful and passionate keynotes. Speakers included Dr K. Radhakrishnan, Former Chairman, Indian Space Research Organisation, Mr Gururaj Deshpande/Sparta Group, Tejas Networks and top leaders from companies like Seagate, MediaTek, Imagination Technologies, Rambus, Intel and others as well as speakers for the different state governments (Chief Minister, Secretary to State etc.). There were panel discussions on "Transforming India – movers shakers", "Fuelling the wheels of change – the essentials", "States – The fulcrum of ESDM Policy implementation", "Realising smart cities with IoT", "Semiconductor Fab – The Opportunity, Challenges Accelerators" and "Building the ESDM start-up ecosystem". The event elicited significant press coverage. Being a part of some of the press briefings, it was heartening to note the interest of the media in this space and especially on the increasing collaboration across countries as a vital path to fast track the growth of the local ESDM ecosystem.    

When the semiconductor industry began the migrated from 200-mm wafers to 300-mm wafers more than a decade ago, chip makers convinced tool suppliers to foot the bill for the RD required to make the move with the promise that they would be justly and richly rewarded with robust sales of the new systems, which much of the industry appeared anxious to adopt. But they were left holding the bag when the dot come bubble burst and—surprise—chip makers decided to delay deployment of 300-mm capacity. Many equipment industry executives were understandably bitter about this. This was in large part the reason that, when chip makers first began making noise about moving to 450-mm wafers a few years ago, the sound you heard was mostly echos and crickets chirping. A lot of people were skeptical right from the beginning that 450-mm would happen at all. Now it appears that 450-mm is inevitable, though the conventional wisdom holds that only a handful of chip makers—notably Intel Corp., Samsung Electronics Co. Ltd., Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and Globalfoundries Inc.—will ever build 450-mm manufacturing lines. Still, right from the start, there has been much debate about how tool suppliers and their customers would divvy up the RD costs associated with moving to the new wafer size. (Bob Johnson of Gartner Inc. said this week that the cumulative cost of 450-mm development will be about $17 billion, about $2 billion of which is being spent this year, though he acknowledged that other estimates vary widely). Some fledgling development efforts are now well underway, including the Global 450 Consortium, a $4.8 billion collaborative effort housed at the Albany NanoTech Complex and backed by the companies mentioned above, as well as IBM Corp. For some tool makers, though, this was not enough. ASML Holding NV, the dominant player in lithography equipment, was largely seen dragging its feet on 450-mm. Moving to 450-mm will require new lithography equipment with more advanced stages that can support the increased size and weight without creating vibrations that would make accurate lithography exposure impossible. Given the fact that no more than a handful of chip makers are expected to buy the new tools, ASML foresaw a limited return on the considerable investment that would be required. ASML of course has now come around, but only after the firm devised an innovative equity-plus-research funding scheme that asks those chip makers with the most to gain from the move to 450-mm wafers—and extreme ultraviolet (EUV) lithography that matter—to foot some of the bill for new technology up front. Last week, Intel announced it would acquire a 15 percent stake in ASML as part of a $4.1 billion deal to accelerate the development of 450-mm and EUV lithography. In addition to paying over $3 billion for the stake in ASML, Intel is also contributing more than $1 billion more directly to the development of the new technologies. Intel, of course, also committed to advanced purchase orders for 450-mm and EUV development and production tools. Samsung, TSMC must pony up ASML is willing to sell another 10 percent of the company to other chip makers who are willing to kick in for the development of 450-mm litho tools and EUV. The firm is currently in discussions with both Samsung and TSMC on taking a piece of the action. If those firms decline to participate, or agree to participate but don't collectively buy the entire 10 percent remaining that ASML is willing to sell, ASML will invite others to participate. (As a condition imposed by ASML, Intel's stake in the company is limited to a maximum of 15 percent.) The whole thing is not unlike a waiter bringing the check before serving the meal. But it had to be this way. ASML was not going to put out the investment required on 450-mm without money up front. And owing to its dominant market share in leading-edge lithography tools, there will be no 450-mm chip production without ASML. Intel has the most to gain from the move to 450-mm. Stacy Smith, the company's chief financial officer, said this week that it expects the move to 450-mm to save the company more than $10 billion in manufacturing costs. Still, Intel alone takes ASML up on its offer, its deep pockets will no doubt also benefit rivals who will then get access to 450-mm and EUV lithography tools. That's where the 15 percent stake comes in. Even if Intel is the only chip firm to directly support ASML's development of these technologies, the world's biggest chip maker will get a piece of the action every time a rival pulls out its checkbook to buy one of the new tools. In the words of a spokesman for ASML, Intel now has real skin in the game and even more interest in seeing the development of these technologies succeed. Whether Samsung, TSMC or any other chip vendor takes ASML up on its offer remains to be seen. On one hand, it can be argued, there is little incentive for them to do so at this point. Especially now that Intel has put its money where its mouth is, there is little doubt that ASML will develop 450-mm tools (though for EUV, the case is far from closed). Once ASML has the tools available, they will presumably be happy to sell them to Samsung, TSMC and anyone else who wants them and has the means to pay. But Samsung and TSMC would be wise to pony up and get involved. When 450-mm tools become available, the leading-edge chip makers will want them ASAP. While there is no publicly disclosed intent to give Intel right of first refusal on new tools—other than those Intel has already committed to buying—come sense dictates that you take care of any part owners of your company before shopping them to the general public. If Samsung and TSMC don't get in on the ground floor (first floor?), they may end up waiting until Intel is pretty sure it has all of the tools it wants before they get their hands on any. Also, Intel's 15 percent stake in ASML—as well as any stake Samsung and TSMC may take—is in non-voting shares. But again, common sense dictates that the customer who is helping to foot the bill for the development of the technology will have a louder voice when it's time to make development decisions. Samsung, TSMC and any other firm that does not get in on the action may find itself outside looking in.