原创 总结一下近10年混饭于半导体电路行业的些许感受11

再来看看逻辑综合工程师的工作，以下是工作描述以及入职要求。

Job Requirements and Qualification

You must have a BSEE or MSEE with at least 5+ years of applicable experience. Demonstrate successful results for multiple ASIC programs, is required. Strong written / verbal communication skills are a must, as you will be working, influencing and collaborating with teams in distributed locations. You will need to be very organized with solid understanding of Synopsys and  Cadence design tools and flows.

Minimum Requirements:

• SOC level Synthesis / STA.
• Experienced with Verilog/VHDL digital design
• Hands on experience with constraints development
• Hands on experience with Synopsys design compiler and ICC
• SoC implementation experience such as full chip level synthesis Pre-P&R timing closure
• Hands on experience with Spyglass rule checking, netlist equivalence checking, and gate-level simulations
• Experience with various synthesis options to optimize the power of the Design.
• Work with Place and Route peers for timing closure
• Good Knowledge of Static Timing Analysis and Place and Route.
• Familiarity with various interface technologies including MIPI, USB, I2C, GPIO, DDR etc
• Familiarity with ASIC design flows for deep sub micron technologies
• Familiarity with FPGA design flow is plus

Preferred Requirements:

• Familiarity with image processing is a strong plus

Responsibilities

In this role, the candidate will work with designers and understand the complexity of the blocks and interfaces. A candidate will work with the ASIC design team and will participate in the development of netlist generation from synthesis. A candidate will also support  the design team to do simulations .

Responsibilities include: reading the RTL code. Generating chip level timing constraints. Validating the RTL inputs.  Analyzing the power for the design and optimizing for speed/area/power.  Understand and drive the pre-synthesis chip-level timing to ensure that synthesis and layout level timing and other specifications can be achieved.

Support chip level verification and physical design timing closure.

这个工作只有一个目的，就是把HDL代码变成网表，这个对于做FPGA来说大多时候就是按一下就自动生成了，对芯片这事做起来并不像说的这么轻松，首先要清晰了解整个芯片的时钟复位电源系统，写出约束文件，把HDL代码用工具转换为netlist，并且分析时序报告，比较网表与代码的逻辑一致性，有些dft插入工作也要在这里完成。这个工作除了要求熟悉电路本身的结构外，主要要求对综合工具有深入了解，并对选用的工艺熟悉。不同的综合策略，得出的网表结果跟所费时间是有差异的，许多年来DC一直是首选工具，每出一个新版本，综合工程师都要看看有什么新搞法。这个职位虽然需要写的代码没有逻辑设计验证那么多，但是一般的设计都要来回综合很多次，大芯片每次所费时间又长，等待的也是很让人痛苦。这个工作需要打交道最多的人是逻辑设计人员跟物理设计人员。

这个职位相对来说属于整个数字流程中要求比较高的岗位，除了对工具的熟悉，一般也要求熟练使用脚本语言。这个岗位基本不会招收刚毕业的学生，大部分是公司内部做逻辑设计的人自学一下然后转岗专门搞这个，一般国内公司里边专业做综合的人数量很少，所以这些人跳槽的话公司都会加钱留住，当然这些人的责任也是重大的，如果芯片挂了，这些人是没法再老板那里交差的。这个岗位基本招聘的都是有些资历的工程师，一般工资都在15k以上。

当然这个职位想转行就比较难点，一般都是混时间久了变成公司的台柱子之一，或者去卖DC，不过貌似国内做DC使用培训销售的就那么几个人吧，不同城市的设计服务中心讲课的都是那个面孔。

数字电路工程师的命运

逻辑综合工程师的命运

数字版图工程师的命运