原创 I2C tHD;DAT

The IIC-Bus Specification电气特性里规定了SDA数据保持时间的最大值（标准模式3.47us，快速模式0.9us）为什么会有最大值这一规定呢？刚开始我觉的非常奇怪，后来在飞利浦的IIC 论坛上看到了有人提出相同的问题，原文如下

Hello,

I have two questions about the tHD;DAT parameter specified in the PCA9541 datasheet. Specifically, I'm wondering why there is a maximum value for it.

1) Say for instance that we run our I2C interface at 5 KHz. Won't we automatically fail the tHD,DAT max of 3.45us? It is not clear to me why there is a minimum AND maximum hold time specified for data.

2) Why is tHD,DAT (MAX) specified for the I2C muxes only? This parameter does not appear in the datasheet for other Philips I2C devices (LED dimmers/blinkers, EEPROMs, etc.). This leads me to believe that tHD,DAT (MAX) is either
a) a documentation error, or
b) specified because of some internal implication specific to the I2C mux parts

Any assistance in clearing up these questions would be greatly appreciated.

Thanks in advance for the help.

该问题没有看见回答，不过有一个相类似的回答，原文如下

The maximum Data hold time is a direct reflection of the data setup time and the maximum rising edge transition time. It comes from the requirement that the data change states only when the clock is low, because data transitions with the SCL high are defined as start or stop conditions.

If the slave stretches the clock low time it must complete the data line switching before it releases the SCL to satisfy the Data set up time.

The maximum Data hold time = SCL minimum pulse width low - ( Data set up time and rising transition time)

Maximum Data hold time = 4.7 us - (0.25 us + 1 us) = 3.45 us for standard mode parts.

Maximum Data hold time for fast mode = 1.3 us - (0.1 us + 0.3 us) = 0.9 us

IIC SPEC里其实有一条注释

The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

这段话说的很清楚，如果你不延长SCL低电平时间的话，该最大值必须遵守，也就是说你如果延长SCL低电平时间，该最大值你可以不遵守。