原创 FPGA Based Logic Analyzer

 2010-7-17 22:39  3875 7 7 分类: FPGA/CPLD

FPGA Based Logic Analyzer

The outcome of this project is a logic analysator for home use.

The project includes the actual analyzer in VHDL (for Spartan 3 FPGA) and a PC Software for the end user. The design employs a FPGA board that can be obtained easily.

Features

16 channels at 200MHz sampling rate
32 channels up to 100MHz sampling rate
state analysis up to 50MHz using external clock
256KSamples memory
noise filter
complex serial and parallel trigger with four stages
externally available sampling clock to drive add-ons (like ADCs)
connects via EIA232/RS232 (works with usb to serial adapters)
Java based viewing software (see PC Client for details)
- I2C & SPI protocol analysis

Hardware

The device uses a Xilinx Spartan 3 Starter Kit (DO-SPAR3-DK) evaluation board manufactured by Digilent. It features a XC3S200-4 FPGA with 4ns propagation delay and 3840 cells. Onboard are 1MByte of 10ns SRAM and plenty connectors that can be used as signal inputs.

To construct a comparable board from scratch would be a tough task for a home project. Especially the really low price of about USD100 makes it pointless to try to compete with this "mass product". All that remains to be done is to program the FPGA. For an overview of the VHDL code see:

FPGA VHDL Model

To learn how to communicate with the analyzer read:

Communications Protocol

Client

A java client is used to access the device from almost any PC with a serial port. The client uses the RXTX library for serial port communications which is available for 34 platforms including Linux, Windows and Solaris.

It has been developed with jdk 1.4.2 but might work with older versions. More information about the client can be found on its page:

Logic Analyzer Client