原创 【博客大赛】Xilinx综合错误ERROR:Xst:899官方解释及我遇到的情况

Description

General Description: 

What type of clock statements does XST support? 

XST does not support the use of a complex condition check inside an always block in Verilog. For example, the following code results in the error below: 

always @( negedge input1 or negedge input2 or posedge clock ) 
begin 
if ( ~input1 | ~input2 )  
begin 
output1 <= 1'b1; 
output2 <= 1'b0; 
end 
else  
begin 
output1 <= input1; 
output2 <= input2 & input1; 
end 
end 

"ERROR:Xst:899 - "file_name", line #: The logic for "net_name" does not match a known FF or Latch template."

Solution

To avoid this error, perform the combinatorial logic outside the always block to remove the complex clock statement from the sensitivity list, and then use that intermediate signal in the sensitivity list of the always block, as follows: 

assign temp = ~input1 | ~input2; 
always @( posedge temp or posedge clock ) 
begin 
if ( temp )  
begin 
output1 <= 1'b1; 
output2 <= 1'b0; 
end 
else  
begin 
output1 <= input1; 
output2 <= input2 & input1; 
end 
end

When you infer hardware from HDL, it is important to keep the type of hardware you want in mind. The XST User Guide contains basic templates for the various types of FPGA/CPLD hardware that can be inferred with HDL code: 

http://support.xilinx.com/support/software_manuals.htm  

If your HDL code is modeled after the templates provided, you should be able to infer the desired hardware. 

Another situation that causes this error (which is unrelated to the first example) is when the reset function in the always block has no effect on the register that will be inferred: 

module misc(clk,rst,in1,out1); 
input clk,rst,in1; 
output[1:0] out1; 
reg[1:0] out1; 

always @(posedge clk or posedge rst) 
begin 
if (rst) 
out1[1] = in1; 
else 
out1 = {in1,in1}; 
end 

endmodule 

 

change to: 

module misc(clk,rst,in1,out1); 

input clk,rst,in1; 
output[1:0] out1; 
reg[1:0] out1; 

always @(posedge clk or posedge rst) 
begin 
if (rst) 
out1[1] = 0; 
else 
out1 = {in1,in1}; 
end 
endmodule


The error message also appears when a dual-edge triggered FF is inferred in any device other than a CoolRunner-II. The CoolRunner-II is the only Xilinx device that contains dual-edge triggered FFs: 
: 

always @(posedge clk or negedge clk) 

:

我遇到的情况是：

always @ (posedgeodd_done or posedgeeven_done) begin
。。。

虽然综合时报错的是其它语句，但经人指点修改这个地方后，综合时不再报错。可见多个上升沿作为敏感源的做法确实不大值得推荐。但这样也不是一定会报错，因为我试过有的程序采用这样的写法也不会报错。