原创 动态电路设计心得

4. Why Dynamic gates require monotonically rising inputs during evaluation?<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />

  Reason:As the following picture.If 1 to 0 when the clk is high.Before A change to 0,the A is 1,clk is high,so the output is 0.Once A is 0,the discharge path to Ground is cut off,but as the clk is high the Pmos is cut off ,there is not precharge path either,so the output can’t become high which is not our wanted result.So we should keep the dynamic gates monotonically rising.