原创 IP内核的新层面

最近一段时间，在FPGA架构和基础软件设计工具上，我们已经花费太多的工夫，这使得我们忽视了构成FPGA库的IP核。现在，是该进行补救的时候了，因为RF Engines为Xilinx和Altera的架构提供了一下新的UWB，而Lattice也为自己的FPGA升级了以太网IP。

We’ve spent enough with FPGA architectures and basic software design tools in recent weeks that we’ve given short shrift to the intellectual property cores making up FPGA libraries.  It’s time to remedy that, because RF Engines has some new UWB offerings for Xilinx and Altera architectures, while Lattice has updated Ethernet IP for its own FPGAs.

RF Engines, based on the Isle of Wight in the UK, has found an intriguing new way to use Ultra-Wideband technology.  Those of you familiar with UWB may recognize it as a technology that promised great in-building bandwidth a few years ago, but got caught up in a standards battle that killed off more than one UWB startup.   RF Engines has another idea in mind.  It has developed its ChannelCore Flex IP as a way of increasing signal-processing performance across multiple channels, thus getting more efficient signal processing for radar, surveillance, etc. than traditional Fast Fourier Transforms.

The key to the ChannelCore Flex IP is that individual channels can be individually modified for bandwidth.  While a traditional FFT can scale to thousands of channels, the RF Engines IP allows designers to maintain control of individual channels, as well as controlling the center frequency of each channel.  Typical core prices range from $10,000 to $40,000, and RF Engines has deliberately structured the IP to be reasonably priced for a mid-range FPGA.  For example, a 500-channel ChannelCore with 200 MHz input and channels ranging in size from 5 kHz to 5 MHz could be implemented on a $100 FPGA.

Lattice, meanwhile, is offering a new Ethernet switch IP core with a difference.  Flexibilis Ethernet Switch, or FES, integrates support for a new protocol, High-availability Seamless Redundancy, or HSR (IEC62439-3).  The protocol allows the low-cost creation of networks with near-instantaneous failover time, and no single point of failure.  Since such networks require tight network timing and synchronization, the IP cores also include support for the IEEE 1588v2 Precision Timing Protocol.

Lattice is offering five versions of Flexibilis for its ECP3 FPGA, because this family of FPGA is aimed at industrial control, and the company figures this sort of highly-redundant Ethernet switch will be popular in applications such as the factory floor.  Two of the IP core versions have full HSR support, in six-port and four-port flavors.  Lattice also will offer a simpler Ethernet switch core without HSR support in eight-, four-, and three-port versions.  This week’s launches should prove that FPGA IP for communications is moving well beyond vanilla-flavored Ethernet or RF links.