原创 为AM335x移植Linux内核主线代码(10)关于AM335x的Ethernet上

只要NAND Boot或者SD卡中烧写了U-Boot，剩下的步骤就顺理成章了，运行在SRAM中的U-Boot能实现各种各样的功能，比如加载存放在各种各样地址上的内核和文件系统镜像。而且U-Boot和Linux Kernel代码同源，风格和编译器都一样，学习前者也对后者有裨益。

高级处理器的外设，有一些是单片机不具备的，比如网卡、声卡、LCD驱动、HDMI，它们比常见的UART、SPI、I2C、TIMER等要复杂很多。我是使用开发板厂家的核心板，根据自己的功能需求重新设计底板，调试的时候U-Boot能帮上大忙。因为它几乎能驱动所有的外设，而且轻量快速，编译烧写都很快。

Finally，项目进行到了使用U-Boot调试网卡的时候。千里之行，始于足下！
第一步，当然是阅读AM335x中关于Ethernet的部分了：

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Chapter 14: Ethernet Subsystem

14.1 Introduction
14.2 Integration
14.3 Function Description
14.4 Software Operation
14.5 Ethernet Subsystem Registers

14.1 Introduction

The 3-port switch gigabit ethernet subsystem provides ethernet packet communication and can be configured as an ethernet switch. It provides the gigabit media independent interface (GMII), reduced gigabit media independent interface (RGMII), reduced media independent interface (RMII), the management data input output (MDIO) for physical layer device (PHY) management.

（飞凌OK335xD的开发板，AR8031就是PHY chip，它一端连接AM335x，一端连接RJ45网络变压器，控制接口则是MDIO。之前我把AR8031称作网卡，但其实网卡EMAC在AM335x内部，AR8031是physical layer device。读取的MAC地址信息，也能够在AM335x的地址映射表中找到。）

14.1.1 Features

The general features of the ethernet switch subsystem are:
 * Two 10/100/1000 Ethernet ports with GMII, RMII and RGMII interfaces
 * Wire rate switching (802.1d)
 * Non Blocking switch fabric
 * Flexible logical FIFO based packet buffer structure
 * Four priority level QOS support (802.1p)
 * CPPI 3.1 compliant DMA controllers
 * Support for IEEE 1588v2 Clock Synchronization (2008 Annex D and Annex F)
        - Timing FIFO and time stamping logic inside the SS
 * Device Level Ring (DLR) Support
 * Address Lookup Engine
        - 1024 addresses plus VLANs
        - Wire rate lookup
        - VLAN support
        - Host controlled time-based aging
        - Spanning tree support
        - L2 address lock and L2 filtering support
        - MAC authentication (802.1x)
        - Receive or destination based Multicast and Broadcast limits
        - MAC address blocking
        - Source port locking
        - OUI host accept/deny feature
 * Flow Control Support (802.3x)
 * EtherStats and 802.3Stats RMON statistics gathering (shared)
 * Support for external packet dropping engine
 * CPGMAC_SL transmit to CPGMAC_SL receive Loopback mode (digital loopback) supported
 * CPGMAC_SL receive to CPGMAC_SL transmit Loobback mode (FIFO loopback) supported
 * Maximum frame size 2016 bytes (2020 with VLAN)
 * 8k (2048 x 32) internal CPPI buffer descriptor memory
 * MDIO module for PHY Management
 * Programmable interrupt control with selected interrupt pacing
 * Emulation Support
 * Programmable transmit later Inter-Packet Gap (IPG)
 * Reset isolation

（几个重要的概念：IE1588v2、GMII、RGMII、RMII、CPPI、Reset isolation等等。）

14.1.2 Unsupported Features
14.2 Integration

This device includes a single instantiation of the three-port Gigabit Ethernet Switch Subsystem (CPSW_3GSS_RG). The switch provides 2 external external ports (port 1 and 2) and an internal CPPI interface port (port 0) with IEEE 1588v2 and 802.1ae support. The subsystem consist of:

 * One instance of the 3-port Gigabit switch CPSW-3G, which contains:
        - 2 CPGMAC_SL 10/100/1000 ethernet port modules with GMII interface
 * Two RGMII interface moudles
 * Two RMII interface modules
 * One MDIO interface modules
 * One Interrupt Controller modules
 * Local CPPI memory of size 8K Bytes        

14.2.1 Ethernet Switch Connectivity Attributes
14.2.2 Ethernet Switch Clock and Reset Management
14.2.3 Ethernet Switch Pin List
14.2.4 Ethernet Switch RMII Clocking Details
14.2.5 GMII Interface Signal Connections and Descriptions
14.2.6 RMII Signal Connections and Descriptions
14.2.7 RGMII Signal Connections and Descriptions

（飞凌使用的PHY芯片是AR8031，正是RGMII接口，因此关于RGMII的引脚定义就需要理解。）

RGMII_TD[3-0]  -- OUT
The transmit data pins are a collection of 4-bits of data.
RGMII_RD0 (* is RGMII_TD0?) is the least-significant bit (LSB).
The signals are valid only when RGMII_TCTL is asserted.

RGMII_TCTL  --  OUT
Transmit Control/enable. The transmit enable signal indicates
that the RGMII_TD pins are generating data for use by the PHY.

RGMII_TCLK  --  OUT
The transmit reference clock will be 125Mhz, 25Mhz,
or 2.5Mhz depending on speed of operation.

RGMII_RD[3-0]  --  IN
The receive data pins are a collection of 4 bits of data.
RGMII_RD (* is RGMII_RD0?) is the least significant bit (LSB).
The signals are valid only when RGMII_RCTL is asserted.

RGMII_RCTL  --  IN
The receive data valid/control signal indicates that the RGMII_RD pins
are nibble data for use by the 3PSW.

RGMII_RCLK -- IN
The receive clock is a continuous clock that provides the timing reference
for receive operations. The clock is generated by the PHY and is 2.5MHz
at 10 Mbps operation and 25MHz at 100 Mbps operation, 125 MHz at 1000
Mbps of operation.

MDIO_CLK -- OUT
Management data clock. The MDIO data clock is sourced by the MDIO
module on the system. It is used to synchronize MDIO data access operation
done on the MDIO pin.

MDIO_DATA -- IN/OUT
MDIO_DATA. MDIO data pin drives PHY management data into and out of the
PHY by way of an access frame consisting of start of frame, read/write
indication, PHY address, register address, and data bit cycles. The MDIO_DATA
pin acts as an output for all but the data bit cycles at which time it is an input
for read operations.

（MDIO，瞅着肿么和I2C这么像呢？都是两线，都是CLK和DATA。区别是I2C多设备总线协议，每个设备在空闲时都是开漏状态，当信号有效时拉低，因此它的速度是受到限制的，actually非常低。而MDIO也是多设备通讯协议，但CLK时钟是推挽输出，DATA在IN和OUT之间切换，因此速度比I2C要快得多。）

（第一次接触MDIO，好像只在PHY芯片上有。）

14.3 Function Description
14.3.1 CPSW_3G Subsystem
14.3.1.1 Interrupt Pacing

The receive and transmit pulse interrupts can be paced. The receive threshold and miscellaneous interrupts are not paced. The interrupt pacing feature limits the number of interrupts that occur during a given period of time. For heavily loaded systems in which interrupts can occur at a very high rate (e.g. 148,800 packets per second for Ethernet), the performance benefit is significant due to minimizing the overhead associated with servicing the interrupt. Interrupt pacing increases the CPU cache hit ratio by minimizing the number of times that large interrupt service routines are moved to and from the CPU instruction cache.

Each CPU receive and transmit pulse interrupt contains an interrupt pacing sub-block (six total). Each sub-block is disabled by default allowing the selected interrupt inputs to pass through unaffected. The interrupt pacing module counts the number of interrupts that occur  over a 1 ms interval of time. At the end of each 1 ms interval, the current number of interrupts is compared with a target number of interrupts (specified by associated maximum number of interrupts register).

Based on the results of the comparison, the length of time during which interrupts are blocked is dynamically adjusted. The 1 ms interval is derived from a 4 us pulse that is created from a prescale counter whose value is set in the int_prescale value int the Int_Control register. The int_prescale value should be written with the number of VBUSP_CLK periods in 4 us. The pacing timer determines the interval during which interrupts are blocked and decrements every 4 us. It is reloaded each time a zero count is reached. The value loaded into the pacing timer is calculated by hardware every 1 ms according to the following algorithm:
        
if (intr_count > 2 * intr_max)
        pace_timer = 255;
else if (intr_count > 1.5 * intr_max)
        pace_timer = last_pace_timer * 2 + 1;
else if (intr_count > 1.0 * intr_max)
        pace_timer = last_pace_timer + 1;
else if (intr_count > 0.05 * intr_max)
        pace_timer = last_pace_timer - 1;
else if (intr_count != 0)
        pace_timer = last_pace_timer / 2;
else
        pace_timer = 0;                                             

If the rate of interrupt inputs is much less than the target interrupt rate specified in the associated maximum interrupts register, then the interrupts is not blocked. If the interrupt rate is greater than the target rate, the interrupt will be "paced" at the rate specified in the interrupt maximum register. The interrupt maximum register should be written with a value between 2 and 63 inclusive indicating the target number of interrupts per milli-second.

（单片机的中断概念是很直接的，当中断条件发生，要么处理，要么忽略；单片机的中断嵌套也不复杂，当中断正在处理的时候另外一个更高优先级的中断发生，则先处理高优先级的中断，再返回来继续处理现在这个。AM335x具备的interrupt pacing是另外一个概念，它是说等攒了几个中断之后，再一起处理，因为如果每次中断都申请CPU，在网卡这样高负载的应用下，会影响CPU的性能。）

（也是因为这样，才有了上面的pace_timer产生策略，由它可知，当负载很高的时候，就积攒更多中断再处理；当负载很低的时候，那就来一个处理一个呗！）

14.3.1.2 Reset Isolation

Reset Isolation for the Ethernet switch on Device is that the switch function of the ethernet IP remains active even in case of all device reset except for POR pin reset and ICEPICK COLD reset. Packet traffic to/from the 3PSW host will be flushed/dropped, but the ethernet switch will remain operational for all traffic between external devices on the switch even though the device is under-going a device reset. Pin mux configuration for ethernet related IO and reference clocks needed by the Ethernet switch IP to be active is controlled by a protected control module bit. If reset isolation is enabled, then only a POR pin or ICEPICK COLD reset event should fully reset the Ethernet switch IP including the actual switch and also the reference clocks and pin mux control specifically associated with the Ethernet IP.

（AM335x提供了一个策略，即Ethernet的复位隔离，除了POR pin reset或者ICEPICK COLD reset之外，其它的复位信号不会改变Ethernet的状态。POR pin reset意为通电复位，ICEPICK COLD reset能够提供和前者一样的复位功能，区别是不改变emulation logic and efuse，它应该是和JTAG仿真器相关的复位信号。）

（那提供这样的reset isolation功能有什么作用呢？比如，当看门狗引发复位时，Ethernet不会复位，它的IO口mux、IP地址等等都不会变，维持的工作状态允许从Ethernet进行唤醒操作。）

14.3.1.2.1 Modes of Operation
14.3.1.3 Interrupts
14.3.1.3.1 Receive Packet Completion Pulse Interrupt (RX_PULSE)
14.3.1.3.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE)
14.3.1.3.3 Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)
14.3.1.3.4 Miscellaneous Pulse Interrupt (MISC_PULSE)
14.3.1.3.4.1 EVNT_PEND (CPTS_PEND) Interrupt
14.3.1.3.4.2 Statistics Interrupt
14.3.1.3.4.3 Host Error Interrupt
14.3.1.3.4.4 MDIO Interrupts

MDIO_LINKINT is set if there is a change in the link state of the PHY corresponding to the address in the PHYADDRMON field of the MDIOUSERPHYSELn register and the corresponding LINKINTENB bit is set. The MDIO_LINKINT event is also captured in the MDIOLINKINTMASKED register. When the GO bit in the MDIOUSERACCESSn registers transitions from 1 to 0, indicating the completion of a user access, and the corresponding USERINTMASKSET bit in the MDIOUSERINTMASKSET register is set, the MDIO_USERINT signal is asserted 1. The MDIO_USERINT event is also captured in the MDIOUSERMASKED register.

（MDIO协议的调试，需要用到这些中断标识。）

14.3.1.4 Embedded Memories
14.3.2 CPSW_G

The CPSW_3G GMII interfaces are compliant to the IEEE Std 802.3 Specification.

The CPSW_3G contains two CPGMAC_SL interfaces (ports1 and 2), one CPPI 3.0 interface Host Port (port 0), Common Platform TIme Sync (CPTS), ALE Engine and CPDMA.

14.3.2.1 Media Independent Interface (GMII)
14.3.2.2 IEEE 1588v2 Clock Synchronization Support
14.3.2.2.1 IEEE 1588v2 Receive Packet Operation
14.3.2.2.1.1 Annex F
14.3.2.2.1.2 Annex D
14.3.2.2.2 IEEE 1588v2 Transmit Packet Operation
14.3.2.2.2.1 Annex F
14.3.2.2.2.2 Annex D

（IEEE 1588v2的关键字是Syschronization，意味着时钟同步。）

14.3.2.3 Device Level Ring (DLR) Support

Device Level Ring (DLR) support is enabled by setting the dlr_en bit in the CPSW_Control register. When enabled, incoming received DLR packets are detected and sent to queue 3 (highest priority) of the egress port(s). If the host port is the egress port for a DLR packet then the packet is sent on the CPDMA Rx channel selected by the p0_dlr_cpdma_ch filed in the P0_Control register. The supervisor node MAC address feature is supported with the dlr_unicast bit in the unicast address table entry.

When set, the dlr_unicast bit causes a packet with the matching destination address to be flooded to the vlan_member_list minus the receive port and minus the host port (the port_number field in the unicast address table entry is a don't care). Matching dlr_unicast packets are flooded regardless of whether the packet is a DLR packet or not. The en_p0_uni_flood bit in the ALE_Control register has no effect on DLR unicast packets. Packets are determined to be DLR packets, as shown:

1. DLR is enabled (dlr_en is set in the switch CPSW_Control register).
2. One of the following sequences is true:
 * The first packet ltype matches vlan_ltype 1 and pX_vlan_ltype1_en is set and the the second packet ltype matches dlr_ltype.
 * The first packet ltype matches vlan_ltype 2 and pX_vlan_ltype2_en is set and the second packet ltype matches dlr_ltype.
 * The first packet ltype matches vlan_ltype1 and pX_vlan_ltype1_en is set and the second packet ltype matches vlan_ltype2 and pX_vlan_ltype2_en is set and the third packet ltype matches dlr_ltype.

（DLR主要是解决以太网的实时性问题，在工控网络里是个很重要的概念。）

14.3.2.4 CPDMA RX and TX Interfaces

The CPDMA submodule is a CPPI 3.0 compliant packet DMA transfer controller. The CPPI 3.0 interface is port 0.

After reset, initialization, and configuration the host may initiate transmit operations. Transmit operations are initiated by host writes to the appropriate transmit channel head descriptor pointer contained in the STATERAM block. The transmit DMA controller then fetches the packet in the packet chain from memory in accordance with CPPI 3.0 protocol. The DMA controller writes the packet into the external transmit FIFO in 64-byte bursts (maximum).

Receive operations are initiated by host writes to the appropriate receive channel head descriptor pointer after host initialization and configuration. The receive DMA controller writes the receive packet data to external memory in accordance with CPPI 3.0 protocol. See the CPPI Buffer Descriptors section for detailed description of Buffer Descriptors.

14.3.2.4.1 CPPI Buffer Descriptors

The buffer descriptor is a central part of the 3PSW Ethernet Subsystem and is how the application software describes Ethernet packets to be sent and empty buffers to be filled with incoming packet data.

Host software sends and receives network frames via the CPPI 3.0 compliant host interface. The host interface includes modules registers and host memory data structures. The host memory data structures are buffer descriptors and data buffers. Buffer descriptors are data structures that contain information about a single data buffer. Buffer descriptors may be linked together to describe frames or queues of frames for transmission of data and free buffer queues available for received data.

Note: The 8k bytes of Ethernet Subsystem CPPI RAM begin at address 0x4a102000 and end at 0x4a103FFF from the 3PSW perspective. The buffer descriptors programmed to access the CPPI RAM memory should use the address range from 0x4a102000.

（和程序相关最紧密的就是这里了，它是数据的构成，包括缓存描述符和数据缓存。缓存描述符的格式和网络传输中报文的格式，是两个不同的概念。缓存描述符不会实际发送出去，它的存在是为了Ethernet自身的功能，和硬件的关联更加紧密。）0

14.3.2.4.1.1 TX Buffer Descriptors
14.3.2.4.1.1.1 CPPI Tx Data Word - 0 (Next Descriptor Pointer)
14.3.2.4.1.1.2 CPPI Tx Data Word - 1 (Buffer Pointer)
14.3.2.4.1.1.3 CPPI Tx Data Word - 2 (Buffer _Offset / Buffer _Length)
14.3.2.4.1.1.4 CPPI Tx Data Word - 3
 * Start of Packet (SOP) Flag
 * End of Packet (EOP) Flag
 * Owner ship    
 * EOQ
 * teardown_Complete
 * pass_crc
 * to_port
 * To_port_enable
 * Packet Length
14.3.2.4.1.2 Rx Buffer Descriptors
14.3.2.4.1.2.1 CPPI Rx Data Word - 0 (next_descriptor_pointer)
14.3.2.4.1.2.2 CPPI Rx Data Word - 1 (buffer_pointer)
14.3.2.4.1.2.3 CPPI Rx Data Word - 2 (Buffuer_Offset / Buffer_Length)
14.3.2.4.1.2.4 CPPI Rx Data Word - 3
 * Start of Packet (SOP) Flag
 * End of Packet (EOP) Flag
 * Ownership (OWNER) Flag
 * End of Queue (EOQ) Flag
 * Teardown Complete (TDOWNCMPLT) Flag
 * Pass CRC (PASSCRC) Flag
 * Long (Jabber) Flag
 * Short (Fragment) Flag
 * Control Flag
 * Overrun Flag
 * Pkt_error Flag
 * rx_vlan_encap
 * from_port
 * Packet Length
 
14.3.2.4.2 Receive DMA Interface
14.3.2.4.2.1 Receive DMA Host Configuration
14.3.2.4.2.2 Receive Channel Teardown
14.3.2.4.3 Transmit DMA Interface
14.3.2.4.3.1 Transmit DMA Host Configuration
14.3.2.4.3.2 Transmit Channel Teardown
14.3.2.4.4 Transmit Rate Limiting
14.3.2.4.5 Command IDLE
14.3.2.5 VLAN Aware Mode
14.3.2.6 VLAN Unaware Mode
14.3.2.7 Address Lookup Engine (ALE)
14.3.2.7.1 Address Table Entry
14.3.2.7.1.1 Free Table Entry
14.3.2.7.1.2 Multicast Address Table Entry
14.3.2.7.1.3 VLAN/Multicast Address Table Entry
14.3.2.7.1.4 Unicast Address Table Entry
14.3.2.7.1.5 OUI Unicast Address Table Entry
14.3.2.7.1.6 VLAN/Unicast Address Table Entry
14.3.2.7.1.7 VLAN Table Entry
14.3.2.7.2 Packet Forwarding Processes
14.3.2.7.2.1 Ingress Filtering Process
14.3.2.7.2.2 VLAN_Aware Lookup Process
14.3.2.7.2.3 VLAN_Unaware Lookup Process
14.3.2.7.2.4 Egress Process
14.3.2.7.3 Learning/Updating/Touching Processes
14.3.2.7.3.1 Learning Progress
14.3.2.7.3.2 Updating Progress
14.3.2.7.3.3 Touching Progress

14.3.2.8 Packet Priority Handling
14.3.2.9 FIFO Memory Control
14.3.2.10 FIFO Transmit Queue Control
14.3.2.10.1 Normal Priority Mode
14.3.2.10.2 Dual Mac Mode
14.3.2.10.3 Rate Limit Mode
14.3.2.11 Packet Padding
14.3.2.12 Flow Control

There are two types of switch flow control - CPPI port flow control and Ethernet port flow control. The CPPI and Ethernet port naming conventions for data flow into and out of the switch are reversed. For the CPPI port (port 0), transmit operations move packets from external memory into the switch and then out to either or both Ethernet transmit port (ports 1 and 2). CPPI receive operations move packets that were received on either or both Ethernet receive ports to external memory.

（上面的VLAN和ALE概念，还是有些难度的，实在看不懂，等到调试过程中再仔细看吧。Ethernet还有流量控制的概念啊，从CPPI port到Ethernet port，或者反过来。艾玛，这比SPI协议的说明文档，实在复杂太多了。。。）
 
14.3.2.12.1 CPPI Port Flow Control
14.3.2.12.2 Ethernet Port Flow Control
14.3.2.12.2.1 Receive Flow Control
14.3.2.12.2.1.1 Collision Based Receive Buffer Flow Control
14.3.2.12.2.1.2 IEEE 802.3x Based Receive Flow Control
14.3.2.12.2.2 Transmit Flow Control
14.3.2.13 Packet Drop Interface
14.3.2.14 Short Gap
14.3.2.15 Switch Latency
14.3.2.16 Emulation Control
14.3.2.17 Software IDLE
14.3.2.18 Software Reset
14.3.2.19 FIFO Loopback

14.3.2.20 CPSW_3G Network Statistics
14.3.2.20.1 Rx-only Statistics Descriptions
14.3.2.20.1.1 Good Rx Frames (Offset = 0h)
14.3.2.20.1.2 Broadcast Rx Frames (Offset = 4h)
14.3.2.20.1.3 Multicast Rx Frames (Offset = 8h)
14.3.2.20.1.4 Pause Rx Frames (Offset = Ch)
14.3.2.20.1.5 Rx CRC Errors (Offset = 10h)
14.3.2.20.1.6 Rx Align/Code Errors (Offset = 14h)
14.3.2.20.1.7 Oversize Rx Frames (Offset = 18h)
14.3.2.20.1.8 Rx Jabbers (Offset = 1Ch)
14.3.2.20.1.9 Undersize (Short) Rx Frames (Offset = 20h)
14.3.2.20.1.10 Rx Fragments (Offset = 24h)
14.3.2.20.1.11 Rx Start of Frame Overruns (Offset = 84h)
14.3.2.20.1.12 Rx Middle of Frame Overruns (Offset = 88h)
14.3.2.20.1.13 Rx DMA Overruns (Offset = 8Ch)
14.3.2.20.1.14 Rx Octets (Offset = 30h)
14.3.2.20.1.15 Net Octets (Offset = 80h)
14.3.2.20.2 Tx-only Statistics Descriptions
14.3.2.20.2.1 Good Tx Frames (Offset = 34h)
14.3.2.20.2.2 Broadcast Tx Frames (Offset = 38h)
14.3.2.20.2.3 Multicast Tx Frames (Offset = 3Ch)
14.3.2.20.2.4 Pause Tx Frames (Offset = 40h)
14.3.2.20.2.5 Collisions (Offset = 48h)
14.3.2.20.2.6 Single Collision Tx Frames (Offset = 4Ch)
14.3.2.20.2.7 Multiple Collision Tx Frames (Offset = 50h)
14.3.2.20.2.8 Excessive Collisions (Offset = 54h)
14.3.2.20.2.9 Late Collisions (Offset = 58h)
14.3.2.20.2.10 Tx Underrun (Offset = 5Ch)
14.3.2.20.2.11 Deferred Tx Frames (Offset = 44h)
14.3.2.20.2.12 Carrier Sense Errors (Offset = 60h)
14.3.2.20.2.13 Tx Octets (Offset = 64h)
14.3.2.20.3 Rx- and Tx-Shared Statistics Descriptions
14.3.2.20.3.1 Rx + Tx 64 Octet Frames (Offset)
14.3.2.20.3.2 Rx + Tx 64-127 Octet Frames (Offset = 6Ch)
14.3.2.20.3.3 Rx + Tx 128-255 Octet Frames (Offset = 70h)
14.3.2.20.3.4 Rx + Tx 256-511 Octet Frames (Offset = 74h)
14.3.2.20.3.5 Rx + Tx 512-1023 Octet Frames (Offset = 78h)
14.3.2.20.3.6 Rx + Tx 1024_Up Octet Frames (Offset = 7Ch)

14.3.3 Ethernet Mac Sliver (CPGMAC_SL)
14.3.3.1 GMII/MII Media Independent Interface
14.3.3.1.1 Data Reception
14.3.3.1.1.1 Receive Control
14.3.3.1.1.2 Receive Inter-Frame Interval
14.3.3.1.2 Data Transmission
14.3.3.1.2.1 Transmit Control
14.3.3.1.2.2 CRC Insertion
14.3.3.1.2.3 MTXER
14.3.3.1.2.4 Adaptive Performance OPtimization (APO)
14.3.3.1.2.5 Inter-Packet-Gap Enforcement
14.3.3.1.2.6 Back Off
14.3.3.1.2.7 Programmable Transmit Inter-Packet Gap
14.3.3.1.2.8 Speed, Duplex, and Pause Frame Support Negotiation
14.3.3.2 Frame Classification

14.3.4 Command IDLE
14.3.5 RMII Interface
14.3.6 RGMII Interface
14.3.6.1 RGMII Receive (RX)
14.3.6.2 In-Band Mode of Operation
14.3.6.3 Forced Mode of Operation
14.2.6.4 RGMII Transmit (TX)

14.3.7 Common Platform Time Sync (CPTS)

The CPTS module is used to facilitate host control of time sync operations. It enables compliance with the IEEE 1588-2008(V2) standard for a precision clock synchronization protocol.

（CPTS，关键词是sync，用在IEEE 1588-2008(v2)上，sync的关键在于时钟。此节暂跳过。）

14.3.8 MDIO

The MII Management I/F module implements the 802.3 serial management to interrogate and control two Ethernet PHYs simultaneously using a shared two-wire bus. Two user access registers to control and monitor up to PHYs simultaneously.

（要调试PHY芯片，必须掌握MDIO接口，通过它能得到很多PHY芯片信息，比盲目的调试要有效率。MDIO是和I2C类似的两线通讯协议，但它比I2C协议的速度要快得多，因为I2C是多设备的开漏输出，而MDIO是推挽输出。Anyway，MDIO是非常重要的！）

（下面这个函数，是MDIO的初始化函数cpsw_mdio_init，它还没有建立和PHY的通信，而是初始化了AM335x关于MDIO的寄存器，以及注册U-Boot里面的设备。）
===================================================
static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
{
        struct mii_dev *bus = mdio_alloc();

        mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
        __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
        
        udelay(1000);
        bus->read = cpsw_mdio_read;
        bus->write = cpsw_mdio_write;
        sprintf(bus->name, name);
        mdio_register(bus);
}
===================================================

14.3.8.1 MII Management Interface Frame Formats

The following tables show the read and write format of the 32-bit MII Management interface frames, respectively.

Table 14-22. MDIO Read Frame Format
 * Preamble             0xFFFFFFFF
 * Start Delimiter      01       
 * Operation Code       10
 * PHY Address          AAAAA
 * Register Address     RRRRR
 * Turnaround           Z0
 * Data                 DDDD.DDDD.DDDD.DDDD
 
Table 14-23. MDIO Write Frame Format
 * Preamble             0xFFFFFFFF
 * Start Delimiter      01
 * Operation Code       00
 * PHY Address          AAAAA
 * Register Address     RRRRR
 * Turnaround           10
 * Data                 DDDD.DDDD.DDDD.DDDD
 
The default or idle state of the two wire serial interface is a logic one. All tri-state drivers should be disabled and the PHY's pull-up resistor will pull the MDIO line to a logic one. Prior to initiating any other transaction, the station management entity shall send a preamble sequence of 32 contiguous logic one bits on the MDIO line with 32 corresponding cycles on MDCLK to provide the PHY with a pattern that it can use to establish synchronization. A PHY shall observe a sequence of 32 contiguous logic one bits on MDIO with 32 corresponding MDCLK cycles before it responds to any other transaction.
 
 * Preamble
 * Start Delimiter
 * Operation Code
 * PHY Address
 * Register Address
 * Turnaround
   An idle bit time during which no device actively drives the MDIO signal shall be inserted between the register address field and the data field of a read frame in order to avoid contention. During a read frame, the PHY shall drive a zero bit onto MDIO for the first bit time following the idle bit and preceding the Data field. During a write frame, the field shall consist of a one bit followed by a zero bit.
 * Data
 
（idle bit，这也是MDIO里面很重要的概念。读操作，在register address field和data field之间插入一个idle bit，然后跟随0 bit，用来避免读冲突；而写操作，就直接使用1 bit和0 bit。idle bit的含义应该是释放io口的控制权，相当于此刻通信设备的两端都处于高阻态。从上面的内容可知，每次MDIO操作，不论读写，都会发送2个字，共8个字节。其中第一个字用来初始化时钟，第二字是控制标识和数据。数据为16位。第二个字和user[0].access的内容有共通之处，但并不相同。）