原创 模块化设计之基于FPGA的简易计算器设计

//数码管扫描模块

module shumaguan(data,i_clk,rst_n,o_seg,o_sel);

 input [23:0]data;
 input i_clk;
 input rst_n;
 output [7:0]o_seg;
 output [2:0]o_sel;

 parameter cnt1_WIDTH = 15;
 parameter cnt1_MAX = 24999;

 reg [cnt1_WIDTH-1 :0] cnt1;
 reg clk_1K;//扫描时钟，1KHz
 reg [2:0]sel_r;//数码管位选
 reg [7:0]seg_r;//数码管段选
 reg [3:0]disp_data;//单位显示数据缓存

 //1KHz时钟分频计数器
 always@(posedge i_clk)
 begin
  if(!rst_n)cnt1<=0;
  else if(cnt1==cnt1_MAX)cnt1<=0;
  else cnt1<=cnt1+1'b1;
 end

 //得到1KHz时钟
 always@(posedge i_clk)
 begin
  if(!rst_n)clk_1K<=0;
  else if(cnt1==cnt1_MAX)
   clk_1K<=~clk_1K;
  else ;
 end

 //位选信号控制
 always@(posedge clk_1K)
 begin
  if(!rst_n)sel_r<=3'd0;
  else
   if(sel_r == 3'd6)
    sel_r<=3'd0;
   else
    sel_r<=sel_r+1'b1;
 end

 //根据不同的数码管位选择不同的待显示数据
 always@(*)
 begin
  case(sel_r)
   0:disp_data<=data[23:20];
   1:disp_data<=data[19:16];
   2:disp_data<=data[15:12];
   3:disp_data<=data[11:8];
   4:disp_data<=data[7:4];
   5:disp_data<=data[3:0];
   default :disp_data<=4'd0;
  endcase
 end

 //数据译码，将待显示数据翻译为符合数码管显示的编码
 always@(disp_data)
 begin
  case(disp_data)
   4'd0:  seg_r<=8'hc0;
   4'd1:  seg_r<=8'hf9;
   4'd2:  seg_r<=8'ha4;
   4'd3:  seg_r<=8'hb0;
   4'd4:  seg_r<=8'h99;
   4'd5:  seg_r<=8'h92;
   4'd6:  seg_r<=8'h82;
   4'd7:  seg_r<=8'hf8;
   4'd8:  seg_r<=8'h80;
   4'd9:  seg_r<=8'h90;
   4'd10: seg_r<=8'h88;
   4'd11: seg_r<=8'h83;
   4'd12: seg_r<=8'hc6;
   4'd13: seg_r<=8'ha1;
   4'd14: seg_r<=8'h86;
   4'd15: seg_r<=8'h8e;
   default : seg_r<=8'hff;
  endcase
 end

 assign o_seg = seg_r;
 assign o_sel = sel_r;

endmodule