TABLE OF CONTENTSCHAPTER 1 INTRODUCTION .................................................................................11.1 Motivation ..........................................................................................................11.2 Organization of the Dissertation ........................................................................11.3 ADC Definition..................................................................................................21.4 ADC Characterization........................................................................................41.4.1 Resolution ..............................................................................................41.4.1.1 Nonlinearity51.4.1.2 Signal to Noise Ratio61.4.1.3 Signal to Noise + Distortion Ratio71.4.1.4 Dynamic Range81.4.1.5 Spurious Free Dynamic Range81.4.2 Sampling Rate........................................................................................91.4.3 Input Bandwidth.....................................................................................91.4.4 Power Supply Rejection Ratio .............................................................101.4.5 Input Capacitance.................................................................................101.4.6 Input Signal Swing...............................................................................101.4.7 Power Dissipation ................................................................................10CHAPTER 2 REVIEW OF ANALOG TO DIGITAL CONVERTERARCHITECTURES.............................................................................122.1 Flash ADC .......................................................................................................122.2 Two Step Flash ADC .......................................................................................142.3 Subranging ADC..............................................................................................162.4 Successive Approximation ADC .....................................................................172.5 Pipelined ADC.................................................................................................192.6 Recirculating ADC...........................................................................................212.7 Oversampled ADC...........................................................................................222.8 Serial ADC.......................................................................................................232.9 Recent Performance Achievements .................................................................24CHAPTER 3 DESIGN TECHNIQUES FOR PIPELINED ANALOGTO DIGITAL CONVERTERS ............................................................433.1 Introduction to the Concept of Pipelined ADCs .............................................433.2 Switched Capacitor DAC and Residue Amplifier............................................473.3 Sources of Error in Pipelined Analog to Digital Converters............................51vii3.3.1 Thermal Noise......................................................................................513.3.2 Comparator Offsets..............................................................................523.3.3 Residue Amplifier Gain Error..............................................................563.3.4 Nonuniform Reference Levels (Nonlinear DAC)...............................613.3.5 Residue Amplifier Nonlinearity...........................................................683.3.6 Incomplete Settling of the Sample and Hold Amplifier Output ..........783.3.6.1 Settling Time of a Single Pole System793.3.6.2 Settling Time of a Critically Damped Two Pole System793.3.6.3 Settling Time of an Underdamped Two PoleSystem803.3.6.4 Settling Time of an Overdamped Two Pole System833.3.6.5 Tabulated Settling Times853.3.7 Sample and Hold Tracking Nonlinearity .............................................863.4 Error Correction Techniques............................................................................983.4.1 Analog Offset Correction.....................................................................983.4.2 Digital Comparator Error Correction.................................................1033.4.3 Analog DAC/Gain Calibration ..........................................................1073.4.4 Capacitor Error Averaging.................................................................1103.4.5 Digital DAC/Gain Calibration ...........................................................113CHAPTER 4 SAMPLE AND HOLD AMPLIFIER ARCHITECTURESAND OPTIMIZATION......................................................................1234.1 MOSFET Models for Transient Analysis .....................................................1234.1.1 Long Channel Model for the MOSFET.............................................1244.1.2 Vertical Field Mobility Degradation..................................................1254.1.3 Velocity Saturation ............................................................................1264.1.4 Subthreshold ......................................................................................1304.1.5 Putting the Models Together..............................................................1304.2 Settling Time Analysis of Switched Capacitor Gain Stages..........................1344.2.1 Single Stage Single Pole Amplifier ...................................................1374.2.1.1 Fixed Current Density1394.2.1.1.1 Minimum Power with Fixed Speed1414.2.2 Telescopic Cascode Amplifier...........................................................1444.2.2.1 Optimization of Current Density to Minimize Power -Fixed Speed and Fixed Feedback Capacitance - ModelIncluding Mobility Degradation, Velocity Saturation,viiiand Subthreshold1494.2.3 Wide-Band Preamplifier Driving a Single Stage Amplifier ..............1554.2.3.1 Optimization to Minimize the Power1614.2.4 Two Stage Amplifier with Standard Miller Compensation ...............1674.2.5 Two Stage Amplifier with Ahuja Style Compensation .....................1754.2.6 Three Stage Amplifier with Nested Miller Compensation ................1874.2.7 Comparison of Topologies.................................................................198Appendix.................................................................................................................2034.A.1 Single Stage Amplifier Optimizations ........................................................2054.A.1.1 Minimum Power with Fixed Speed ................................................2064.A.1.2 Maximum Speed with Fixed Feedback Capacitance......................2094.A.1.3 Speed and Power Optimization with Variable Current Density-LongChannel Model...................................................................................2114.A.1.3.1 Speed and Power Optimization with Variable FeedbackCapacitance2144.A.1.3.2 Special Case: No Output Parasitic Capacitance2194.A.2 Telescopic Cascode Amplifier Optimizations.............................................2204.A.2.1 Optimization of Feedback Capacitance to Minimize Power - FixedCurrent Density and Speed ................................................................2214.A.2.1.1 Results of Optimization Using the Long ChannelModel221CHAPTER 5 OPTIMIZATION TECHNIQUES FOR PIPELINEDANALOG TO DIGITAL CONVERTERS.........................................2275.1 Pipelined Analog to Digital Converter Design in the Absence of Noise.......2275.1.1 Optimum Sampling Capacitor Size to Minimize Pipeline Power .....2275.1.2 Optimum Number of Bits Per Stage to Minimize Pipeline Power ....2365.2 Pipelined Analog to Digital Converter Design in the Presence of Noise ......2395.2.1 Thermal Noise in Switched Capacitor Gain Blocks ..........................2415.2.1.1 Thermal Noise Contribution of the Sampling Switches(kT/C Noise)2415.2.1.2 Thermal Noise Contribution of the TransconductanceAmplifier2435.2.1.2.1 Thermal Noise of a Single StageAmplifier2445.2.1.2.2 Thermal Noise of a Critically DampedTelescopic Cascode Amplifier2475.2.1.2.3 Thermal Noise of a PreamplifierixDriving a Single Stage Amplifier2485.2.1.2.4 Thermal Noise of a Two Stage MillerCompensated Amplifier2515.2.1.2.5 Thermal Noise of an Amplifier with AhujaStyle Compensation2545.2.2 Optimal Capacitor Sizing in High Resolution-Low Speed PipelinedAnalog to Digital Converters .............................................................2565.2.3 Optimal Closed Loop Gain of Interstage Gain Amplifiers in High Resolution-High Speed Pipelined Analog to Digital Converters ............2645.2.4 Optimum Closed Loop Gain of Interstage Gain Amplifiers in a PipelinedADC with Parasitics Included...................................................2735.2.5 Optimum Supply Voltage for Power Dissipation in a PipelinedADC...................................................................................................2805.2.5.1 Thermal Noise Limits to Power Dissipation in a PipelinedADC2815.2.5.2 Power Dissipation Trade-offs in Choosing the SupplyVoltage2835.3 Scaling of Power and Speed in an Optimized Pipelined ADC ......................289Appendix.................................................................................................................295CHAPTER 6 PROTOTYPE DESIGN AND DESCRIPTION.................................3176.1 Design Goal ...................................................................................................3176.2 Architecture....................................................................................................3176.2.1 Comparator Architecture ...................................................................3176.2.2 Encoding Network .............................................................................3236.2.2.1 Voting Error Correction3236.2.2.2 Digital to Analog Converter3246.2.3 Sample and Hold Amplifier Architecture ..........................................3326.2.4 Operational Amplifier Architecture...................................................3346.2.5 Bias Circuit for the Operational Amplifier ........................................3366.2.6 Clock Generation ...............................................................................3416.2.7 Layout Considerations .......................................................................3446.2.7.1 Sampling Capacitor Layout3446.2.7.2 Interconnect Layout3466.3 Power Supply Noise Issues ............................................................................348CHAPTER 7 EXPERIMENTAL RESULTS ...........................................................3577.1 Die Photograph ..............................................................................................3577.2 Code Density Test ..........................................................................................358x7.3 Signal to Noise Ratio and Distortion .............................................................3637.3.1 Results for Low Input Frequency (100kHz) ......................................3647.3.2 Results for High Input Frequency (2MHz)........................................3657.3.3 Signal to Noise Ratio Versus Input Amplitude..................................3667.3.4 Idle Channel Noise.............................................................................3687.4 Summary of Results.......................................................................................368CHAPTER 8 CONCLUSIONS AND FUTURE WORK........................................3718.1 Conclusions....................................................................................................3718.1.1 Optimization of Pipelined ADCs .......................................................3718.1.2 Opamp Architectures for Switched Capacitor Applications..............3738.2 Pipelined ADC with Low Swing Amplifiers and Extra Comparators ..........374……