AIF_Framework\AIF_F1.............\......\AIF_F1.CS_.............\......\AIF_F1.pjt.............\......\ConfigurationF1.tcf.............\......\Debug.............\......\.....\AIF_F1.out.............\......\TCI6488_F1.cmd.............\AIF_F2.............\......\AIF_F2.CS_.............\......\AIF_F2.pjt.............\......\ConfigurationF2.tcf.............\......\Debug.............\......\.....\AIF_F2.out.............\......\TCI6488_F2.cmd.............\evmTCI6488.zip.............\inc.............\...\aif_Antenna_Data.h.............\...\aif_Control_Words.h.............\...\aif_debug.h.............\...\aif_edma.h.............\...\aif_fsync.h.............\...\aif_intc.h.............\...\aif_PS_Data.h.............\...\aif_setup.h.............\...\aif_test_config.h.............\...\aif_timer.h.............\Readme.txt.............\src.............\...\aif_Antenna_Data.c.............\...\aif_Control_Words.c.............\...\aif_debug.c.............\...\aif_edma.c.............\...\aif_fsync.c.............\...\aif_intc.c.............\...\aif_main.c.............\...\aif_PS_Data.c.............\...\aif_setup.c.............\...\aif_Test_Config.c.............\...\aif_timer.c.............\...\psc_util.cThe steps to run the codes are:1, Make sure JP8 on the EVM is shorted. Press the PORz Button on the EVM to Reset it. This is not required for first time after power up, but it is required to re-run the program without power cycle.2, Conncet CCS to the DSP. GEL file should be loaded to make DSP run at 1GHz.3, Load AIF_F1 to core 0 of F1 (Faraday DSP1)4, Load AIF_F2 to core 0 of F2 (Faraday DSP2)5, Run F2 firstly, then run F1Check the LOG0 of DSP/BIOS on F1 for test result, the configuration and status information for every link are also shown in the LOG. The correct result at the end of the LOG should like following for OBSAI mode: Link1 transferred 15000 CS data blocks, 15360000 chips CS data received 300 error CS data blocks, 14700 consecutive correct CS data blocks transferred 190000 PS messages, received 188000 PS messagesThe correct result at the end of the LOG should like following for CPRI mode: Link1 transferred 15000 CS data blocks, 11520000 chips CS data received 150 error CS data blocks, 14850 consecutive correct CS data blocks transferred 15000 CPRI control hyper frame, received 14850 good CPRI control hyper framePlease note, the 300 or 150 error buffers actually happen at the beginning during link synchronization, which is normal.There are two projects for two DSPs, the project in .\ AIF_F1 runs on F1 (Faraday DSP 1), the project in .\ AIF_F2 runs on F2 (Faraday DSP 2). Both projects share same codes files in .\src and .\inc directories. The codes for different DSPs are differentiated by macro definition like following:#ifdef _EVM_F1#include "ConfigurationF1cfg.h"#else#include "ConfigurationF2cfg.h"#endifThe project for F1 is built with _EVM_F1 macro defined; the project for F2 is built with _EVM_F2 macro defined.User can change the initialization values of basic configuration structure in aif_Test_Config.c as following and rebuild the project to verify most functionalities of AIF.//Change this parameter to switch between OBSAI/CPRI testCSL_AifLinkProtocol aifProtocol= CSL_AIF_LINK_PROTOCOL_CPRI;/*CPRI control word mode*/CSL_AifCpriCtrlWMode cpriCtrlWordMode= CSL_AIF_CPRI_CTRL_WORD_READ_FROM_RAM; /*Change following basic parameters to switch between different test modes*/AifConfig aifConfig[6]={/*without external connection, link 0 can only be used for internal loop back test*/{ 0, /*linkIndex , do not change this field */0, /*Line Enable: 1=enable, 0=disable*/1, /*linkRate: 1=1x; 2=2x; 4= 4x*/TEST_PATH_INTERLNAL_LOOPBACK, /*test data path*/CSL_AIF_LINK_DATA_TYPE_DL, /*outboundDataType*/CSL_AIF_DATA_WIDTH_16_BIT, /*outboundDataWidth*/CSL_AIF_LINK_DATA_TYPE_DL, /*inboundDataType*/CSL_AIF_DATA_WIDTH_16_BIT, /*inboundDataWidth*/},/*Configuration for link 1*/{ 1, /*linkIndex , do not change this field */1, /*Line Enable: 1=enable, 0=disable*/1, /*linkRate: 1=1x; 2=2x; 4= 4x*/TEST_PATH_REDIRECTION, /*test data path*/CSL_AIF_LINK_DATA_TYPE_DL, /*outboundDataType*/CSL_AIF_DATA_WIDTH_16_BIT, /*outboundDataWidth*/CSL_AIF_LINK_DATA_TYPE_DL, /*inboundDataType*/CSL_AIF_DATA_WIDTH_16_BIT, /*inboundDataWidth*/},…………/*Configuration for link 3*/{ 3, /*linkIndex , do not change this field */1, /*Line Enable: 1=enable, 0=disable*/4, /*linkRate: 1=1x; 2=2x; 4= 4x*/TEST_PATH_REDIRECTION_AGGREGATION, /*test data path*/CSL_AIF_LINK_DATA_TYPE_UL_RSA, /*outboundDataType*/CSL_AIF_DATA_WIDTH_8_BIT, /*outboundDataWidth*/CSL_AIF_LINK_DATA_TYPE_UL_RSA, /*inboundDataType*/CSL_AIF_DATA_WIDTH_8_BIT, /*inboundDataWidth*/},…………};Because of L2 RAM bandwidth and CPU loading limitation, more than 3 4x full-duplex links can not be simultaneously run for this test. But if you mix 1x, 2x, 4x link rate for different links, you can run more than 3 links simultaneously. To rebuild the project with your new configurations, you may need to:1, change the CSL directory2, install an DSP/BIOS template used by this project. Please unzip evmTCI6488.zip in the directory of the project, then copy the “evmTCI6488” directory to .\CCStudio_v3.3\bios_5_31_02\packages\ti\platforms”.……