Design and optimization of CMOS RF power amplifiers166 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 2, FEBRUARY 2001 Design and Optimization of CMOS RF Power Amplifiers Ravi Gupta, Associate Member, IEEE, Brian M. Ballweber, Member, IEEE, and David J. Allstot, Fellow, IEEE Abstract―A CMOS radio-frequency power amplifier including on-chip matching networks has been designed in a 0.6- m n-well triple-metal digital CMOS process, and optimized using a simulated-annealing-based custom computer-aided design tool. A compact inductor model enables the incorporation of parasitics as an integral part of the parasitic-aware design and CAD optimization; low-Q metal3 spiral inductors are used in the input and output matching networks. A 3-V 85 -mW balanced fully integrated Class-C power amplifier with a measured drain efficiency of 55% at 900 M……