PLLjitterThe Designer’s Guide Community downloaded from www.designers-guide.org Modeling Jitter in PLL-based Frequency Synthesizers Ken Kundert Designer’s Guide Consulting, Inc. Version 4g, August 2006 A methodology is presented for modeling the jitter in a Phase-Locked Loop (PLL) that is both accurate and efficient. The methodology begins by characterizing the noise behavior of the blocks that make up the PLL using transistor-level simulation. For each block, the jitter is extracted and provided as a parameter to behavioral models for inclusion in a high-level simulation of the entire PLL. This approach is efficient enough to be applied to PLLs acting as frequency synthesizers with large divide ratios. Last updated on August 30, 2006. You can find the most recent version at www.designersguide……