低电压CMOS模拟集成运算放大器输入级的研究第 27 卷　第 4 期 2004 年 12 月 电　子　器　件 Ch inese Jou rna l of E lect ron D evices Vol . 27　N o. 4 D ec. 2004 The Research of Input Stage of L ow Voltage CM O S Ana log In tegra ted C ircu it Am pl if ier YU X ue2g ang , CH EN G M eng 2z hang (H ua ian C olleg e of Inf orm a tion T echnology , H ua ian 223001, C h ina ) Abstract: T he p rob lem s of inp u t stage of low vo ltage CM O S ana log in teg ra ted circu it am p lifier a re T h ree so lving m ethod s w h ich includes R a il2to 2 R a il d ifferen t ia l inp u t stage, stab le t ran sconductance d ifferen t ia l inp u t stage (A ssum e KN = KP ) and stab le t ran sconductance d ifferen t ia l in t roduced. inp u t stage (A ssum e KN ≠ KP ) a re d iscu ssed. T he m o re resp ect ing p rob lem s of inp u t stage of low vo ltage CM O S ana……