Verification Avenueverificationavenue The Synopsys technical bulletin for design and verification engineers Vol. 6, Issue 3, October 2006 SystemVerilog-OpenVera Interoperability in VCS Alex Wakefield, Synopsys, Inc. Shekhar Mahatme, Synopsys, Inc. Janick Bergeron, Synopsys, Inc. Introduction SystemVerilog is the first industrystandard language to combine highlevel verification constructs with design and modeling constructs in the same language. Much of the verification and testbench technology in SystemVerilog was based on Synopsys’ donation of the OpenVera language to Accellera, providing a solid implementation to prove the utility and effectiveness of these enhancements. With SystemVerilog, verification engineers have a single integrated language supporting the methodologies that Vera tool users have used……