xilinxFPGA开发PCIeBMDDMA的verilogHDL源码
时间:2019-12-19
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BMD\BMD_128_RX_ENGINE.v...\BMD_128_TX_ENGINE.v...\BMD_32_RX_ENGINE.v...\BMD_32_TX_ENGINE.v...\BMD_64_RX_ENGINE.v...\BMD_64_TX_ENGINE.v...\common\BMD.v...\......\BMD_CFG_CTRL.v...\......\BMD_EP.v...\......\BMD_EP_MEM.v...\......\BMD_EP_MEM_ACCESS.v...\......\BMD_GEN2.v...\......\BMD_INTR_CTRL.v...\......\BMD_INTR_CTRL_DELAY.v...\......\BMD_PCIE_20.v...\......\BMD_RD_THROTTLE.v...\......\BMD_TO_CTRL.v...\pipe_1_lane_pci_exp_32b_app.v...\s6_pci_exp_32b_app.v...\UCCmds32.cmf...\v5_blk_plus_pci_exp_64b_app.v...\v6_pci_exp_128b_app.v...\v6_pci_exp_64b_app.v...\common……
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